Analysis and Design of Radio Frequency Integrated Circuits for Breast Cancer Radar Imaging in CMOS Technology

Breast cancer is by far the most incident tumor among female population. Early stage prevention is a key factor in delivering long term survival of breast cancer patients. X-ray mammography is the most commonly used diagnostic technique to detect non-palpable tumors. However, 10-30% of tumors are missed by mammography and ionizing radiations together with breast compression do not lead to comfort in patient treatment. In this context, ultrawideband microwave radar technology is an attractive alternative. It relies on the dielectric contrast of normal and malignant tissues at microwave frequencies to detect and locate tumors inside the breast. This work presents the analysis and design of radio frequency integrated circuits for breast cancer imaging in CMOS technology. The first part of the thesis concerns the system analysis. A behavioral model of two different transceiver architectures for UWB breast cancer imaging employing a SFCW radar system are presented. A mathematical model of the direct conversion and super heterodyne architectures together with a numerical breast phantom are developed. FDTD simulations data are used to on the behavioral model to investigate the limits of both architectures from a circuit-level point of view. Insight is given into I/Q phase inaccuracies and their impact on the quality of the final reconstructed images. The result is that the simplicity of the direct conversion architecture makes the receiver more robust toward the critical impairments for this application. The second part of the thesis is dedicated to the circuit design. The main achievement is a 65nm CMOS 2-16GHz stepped frequency radar transceiver for medical imaging. The RX features 36dB conversion gain, >29dBm compression point, 7dB noise figure, and 30Hz 1/f noise corner. The TX outputs 14dBm with >40dBc harmonic rejection and <109dBc/Hz phase noise at 1MHz offset. Overall power dissipation is 204mW from 1.2V supply. The radar achieves 3mm resolution within the body, and 107dB dynamic range, a performance enabling the use for breast cancer diagnostic imaging. To further assess the capabilities of the proposed radar, a physical breast phantom was synthesized and two targets mimicking two tumors were buried inside the breast. The targets are clearly identified and correctly located, effectively proving the performance of the designed radar as a possible tool for breast cancer detection

Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers

In wireless communication industry, the convergence of stand-alone, single application transceiver IC’s into scalable, programmable and platform based transceiver ICs, has led to the possibility to create sophisticated mobile devices within a limited volume. These multi-standard (multi-mode), MIMO, SDR and cognitive radios, ask for more adaptability and flexibility on every abstraction level of the transceiver. The adaptability and flexibility of the receive paths require a digitized receiver architecture in which most of the adaptability and flexibility is shifted in the digital domain. This trend to ask for more adaptability and flexibility, but also more performance, higher efficiency and an increasing functionality per volume, has a major impact on the IP blocks such systems are built with. At the same time the increasing requirement for more digital processing in the same volume and for the same power has led to mainstream CMOS feature size scaling, leading to smaller, faster and more efficient transistors, optimized to increase processing efficiency per volume (smaller area, lower power consumption, faster digital processing). As wireless receivers is a comparably small market compared to digital processors, the receivers also have to be designed in a digitally optimized technology, as the processor and transceiver are on the same chip to reduce device volume. This asks for a generalized approach, which maps application requirements of complex systems (such as wireless receivers) on the advantages these digitally optimized technologies bring. First, the application trends are gathered in five quality indicators being: (algorithmic) accuracy, robustness, flexibility, efficiency, and emission, of which the last one is not further analyzed in this thesis. Secondly, using the quality indicators, it is identified that by introducing (or increasing) digitization at every abstraction level of a system, the advantages of modern digitally optimized technologies can be exploited. For a system on a chip, these abstraction levels are: system/application level, analog IP architecture level, circuit topology level and layout level. In this thesis, the quality indicators together with the digitization at different abstraction levels are applied to S¿ modulators. S¿ modulator performance properties are categorized into the proposed quality indicators. Next, it is identified what determines the accuracy, robustness, flexibility and efficiency of a S¿ modulator. Important modulator performance parameters, design parameter relations, and performance-cost relations are derived. Finally, several implementations are presented, which are designed using the found relations. At least one implementation example is shown for each level of digitization. At system level, a flexible (N)ZIF receiver architecture is digitized by shifting the ADC closer to the antenna, reducing the amount of analog signal conditioning required in front of the ADC, and shifting the re-configurability of such a receiver into the digital domain as much as possible. Being closer to the antenna, and because of the increased receiver flexibility, a high performance, multi-mode ADC is required. In this thesis, it is proven that such multi-mode ADCs can be made at low area and power consumption. At analog IP architecture level, a smarter S¿ modulator architecture is found, which combines the advantages of 1-bit and multi-bit modulators. The analog loop filter is partly digitized, and analog circuit blocks are replaced by a digital filter, leading to an area and power efficient design, which above all is very portable, and has the potential to become a good candidate for the ADC in multimode receivers. At circuit and layout level, analog circuits are designed in the same way as digital circuits are. Analog IP blocks are split up in analog unit cells, which are put in a library. For each analog unit cell, a p-cell layout view is created. Once such a library is available, different IP blocks can be created using the same unit cells and using the automatic routing tools normally used for digital circuits. The library of unit cells can be ported to a next technology very quickly, as the unit cells are very simple circuits, increasing portability of IP blocks made with these unit cells. In this thesis, several modulators are presented that are designed using this digital design methodology. A high clock frequency in the giga-hertz range is used to test technology speed. The presented modulators have a small area and low power consumption. A modulator is ported from a 65nm to a 45nm technology in one month without making changes to the unit cells, or IP architecture, proving that this design methodology leads to very portable designs. The generalized system property categorization in quality indicators, and the digitization at different levels of system design, is named the digital design methodology. In this thesis this methodology is successfully applied to S¿ modulators, leading to high quality, mixed-signal S¿ modulator IP, which is more accurate, more robust, more flexible and/or more efficient