Energy-Aware Variable Partitioning and Instruction Scheduling for Multibank Memory Architectures

Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures presents a great challenge to compiler design. In this article, we present an approach for variable partitioning and instruction scheduling to maximally exploit the benefits provided by such architectures. Our approach is built on a novel graph model which strives to capture both performance and power demands. We propose an algorithm to iteratively find the variable partition such that the maximum energy saving is achieved while satisfying the given performance constraint. Experimental results demonstrate the effectiveness of our approach. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors—Compilers;C.3[Special-Purpose and Application-Based Systems]—Signal processing systems;B.5.1 [Register-Transfer-Level Implementation]: Design—Memory desig