End-to-End Validation of Architectural Power Models

While researchers have invested substantial effort to build architectural power models, validating such models has proven difficult at best. In this paper, we examine the accuracy of commonly used architectural power models on a custom ASIC microprocessor. Our platform is the TRIPS system for which we have readily available high-level simulators, RTL simulators, and hardware. Access to all three levels of the design provides insight that is missing from previous published studies. First, we show that applying common architectural power models out-of-the-box to TRIPS results in an underestimate of the total power by 65%. Next, using a detailed breakdown of an accurate RTL power model (6 % average error), we identify and quantify the major sources of inaccuracies in the architectural power model. Finally, we show how fixing these sources of errors decreases the inaccuracy to 24%. While further reductions are difficult due to systematic modeling error in the simulator, we conclude with recommendations to improve architectural level power modeling.