1 research outputs found
Integrating simultaneous bi-direction signalling in the test fabric of 3D stacked integrated circuits.
Jennions, Ian K. - Associate SupervisorThe world has seen significant advancements in electronic devices’ capabilities,
most notably the ability to embed ultra-large-scale functionalities in lightweight,
area and power-efficient devices. There has been an enormous push towards
quality and reliability in consumer electronics that have become an indispensable
part of human life. Consequently, the tests conducted on these devices at the
final stages before these are shipped out to the customers have a very high
significance in the research community. However, researchers have always
struggled to find a balance between the test time (hence the test cost) and the
test overheads; unfortunately, these two are inversely proportional.
On the other hand, the ever-increasing demand for more powerful and compact
devices is now facing a new challenge. Historically, with the advancements in
manufacturing technology, electronic devices witnessed miniaturizing at an
exponential pace, as predicted by Moore’s law. However, further geometric or
effective 2D scaling seems complicated due to performance and power concerns
with smaller technology nodes. One promising way forward is by forming 3D
Stacked Integrated Circuits (SICs), in which the individual dies are stacked
vertically and interconnected using Through Silicon Vias (TSVs) before being
packaged as a single chip. This allows more functionality to be embedded with a
reduced footprint and addresses another critical problem being observed in 2D
designs: increasingly long interconnects and latency issues. However, as more
and more functionality is embedded into a small area, it becomes increasingly
challenging to access the internal states (to observe or control) after the device
is fabricated, which is essential for testing. This access is restricted by the limited
number of Chip Terminals (IC pins and the vertical Through Silicon Vias) that a
chip could be fitted with, the power consumption concerns, and the chip area
overheads that could be allocated for testing.
This research investigates Simultaneous Bi-Directional Signaling (SBS) for use
in Test Access Mechanism (TAM) designs in 3D SICs. SBS enables chip
terminals to simultaneously send and receive test vectors on a single Chip
Terminal (CT), effectively doubling the per-pin efficiency, which could be
translated into additional test channels for test time reduction or Chip Terminal
reduction for resource efficiency. The research shows that SBS-based test
access methods have significant potential in reducing test times and/or test
resources compared to traditional approaches, thereby opening up new avenues
towards cost-effectiveness and reliability of future electronics.PhD in Manufacturin