A 0.45V continuous time-domain filter using asynchronous oscillator structures

This paper presents a novel oscillator based filter structure for processing time-domain signals with linear dynamics that extensively uses digital logic by construction. Such a mixed signal topology is a key component for allowing efficient processing of asynchronous time encoded signals that does not necessitate external clocking. A miniaturized primitive is introduced as analogue time-domain memory that can be modelled, synthesized, and incorporated in closed loop mixed signal accelerators to realize more complex linear or non-linear computational systems. This is contextualized by demonstrating a compact low power filter operating at 0.45 V in 65 nm CMOS. Simulation results are presented showing an excess of 50 dB dynamic range with a FOM of 7fJ/pole which promises an order of magnitude improvement on state-of-the-art filters in nanometre CMOS

Hybrid-Phase-Transition FET Devices for Logic Computation

Hybrid-phase-transition FETs (HyperFETs), built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON-to- OFF current ratio. In this article, we describe a comprehensive study carried out to explore the potential of these devices for low-power and energy-limited logic applications. HyperFETs with different ON-OFF current tradeoffs are evaluated at the circuit level. The results show limited improvement over conventional transistors in terms of power and energy. However, based on this analysis, this article proposes different design techniques to overcome the drawbacks identified in the study and thereby make better use of HyperFETs. Hybrid circuits, using both FinFETs and HyperFETs, and circuits combining different HyperFET devices are introduced and evaluated. At some frequencies, reductions of over 40% were obtained with respect to FinFET-only implementations, while minimum energy per operation values were obtained, which were lower than those achieved with low standby power (LSTP) FinFETs and high-performance (HP) FinFETs. This article also evaluates the impact of PTM transition time on the power performance of HyperFET circuits.Ministerio de Economía y Competitividad, FEDER TEC2017-87052-

TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations

Accommodating all the weights on-chip for large-scale NNs remains a great challenge for SRAM based computing-in-memory (SRAM-CIM) with limited on-chip capacity. Previous non-volatile SRAM-CIM (nvSRAM-CIM) addresses this issue by integrating high-density single-level ReRAMs on the top of high-efficiency SRAM-CIM for weight storage to eliminate the off-chip memory access. However, previous SL-nvSRAM-CIM suffers from poor scalability for an increased number of SL-ReRAMs and limited computing efficiency. To overcome these challenges, this work proposes an ultra-high-density three-level ReRAMs-assisted computing-in-nonvolatile-SRAM (TL-nvSRAM-CIM) scheme for large NN models. The clustered n-selector-n-ReRAM (cluster-nSnRs) is employed for reliable weight-restore with eliminated DC power. Furthermore, a ternary SRAM-CIM mechanism with differential computing scheme is proposed for energy-efficient ternary MAC operations while preserving high NN accuracy. The proposed TL-nvSRAM-CIM achieves 7.8x higher storage density, compared with the state-of-art works. Moreover, TL-nvSRAM-CIM shows up to 2.9x and 1.9x enhanced energy-efficiency, respectively, compared to the baseline designs of SRAM-CIM and ReRAM-CIM, respectively