Lower bounds for dilation, wirelength, and edge congestion of embedding graphs into hypercubes

Interconnection networks provide an effective mechanism for exchanging data between processors in a parallel computing system. One of the most efficient interconnection networks is the hypercube due to its structural regularity, potential for parallel computation of various algorithms, and the high degree of fault tolerance. Thus it becomes the first choice of topological structure of parallel processing and computing systems. In this paper, lower bounds for the dilation, wirelength, and edge congestion of an embedding of a graph into a hypercube are proved. Two of these bounds are expressed in terms of the bisection width. Applying these results, the dilation and wirelength of embedding of certain complete multipartite graphs, folded hypercubes, wheels, and specific Cartesian products are computed

Queue Layout of Planar 3−Tree

Graph drawing is essential for data representation. This thesis addresses various graph drawing techniques, their implementation, and enhancements. First, we discuss the 3D grid drawing techniques. The subsequent chapters address the Stack Layout and Queue layout of the graph. The application of Stack and Queue layout and its importance also discussed. Section 4, dedicated to outerplanar Graph. In this chapter, we have discussed how outerplanar Graphs are implemented and their queue and track layouts. The most important part of this thesis is chapter 5, in which the implementation of planar 3-Tree is given. An outerPlanar graph and Planar 3-Tree are internally related. The known upper bound of the queue number of planar 3-Tree is 7. We have implemented the queue layout of 2-Layer planar 3-Tree using two queues and then generalized this experiment for any arbitrary number of levels