NanoMagnet Logic: an Architectural Viewpoint

Among the possible implementation of Field- Coupled devices NanoMagnet Logic is attractive for its low power consumption and the possibility to combine memory and logic in the same device. However, the nature of these technologies is so different from CMOS transistors that the implications on the circuit architecture must be taken carefully into account. In this work we analyze the most important issues related to the design of complex circuits using this technology. We discuss how they influence the architectural level. We propose detailed solutions to solve these problems and to improve the overall performance. As a result of this analysis the type of circuits and applications that constitute the best target for this technology are identified. The analysis is performed on NanoMagnet Logic but the results can be applied to any QCA technolog

Electron Spin for Classical Information Processing: A Brief Survey of Spin-Based Logic Devices, Gates and Circuits

In electronics, information has been traditionally stored, processed and communicated using an electron's charge. This paradigm is increasingly turning out to be energy-inefficient, because movement of charge within an information-processing device invariably causes current flow and an associated dissipation. Replacing charge with the "spin" of an electron to encode information may eliminate much of this dissipation and lead to more energy-efficient "green electronics". This realization has spurred significant research in spintronic devices and circuits where spin either directly acts as the physical variable for hosting information or augments the role of charge. In this review article, we discuss and elucidate some of these ideas, and highlight their strengths and weaknesses. Many of them can potentially reduce energy dissipation significantly, but unfortunately are error-prone and unreliable. Moreover, there are serious obstacles to their technological implementation that may be difficult to overcome in the near term. This review addresses three constructs: (1) single devices or binary switches that can be constituents of Boolean logic gates for digital information processing, (2) complete gates that are capable of performing specific Boolean logic operations, and (3) combinational circuits or architectures (equivalent to many gates working in unison) that are capable of performing universal computation.Comment: Topical Revie

Modeling, Design, and Analysis of MagnetoElastic NML Circuits

With the predicted end of CMOS scaling process, researchers started to study several alternative technologies. Among them NanoMagnet Logic (NML) offers advantages complementary to MOS transistors especially for its magnetic nature. Its intrinsic memory capability makes it suitable for zero stand-by power and logic-in-memory applications. NML requires a clock system that, if based on a magnetic field, highly increases the circuit dynamic power consumption. We have recently proposed a solution based on the magnetoelastic effect (ME-NML) [1] and on currently available fabrication processes, which drastically reduces dynamic power consumption. However, many questions still remain unanswered. Which kind of applications are best suited for this technology? How can we effectively design, analyze, and compare ME-NML circuits? Does it really offer advantages over state-of-the-art CMOS transistors? In this paper, we provide answers to all these questions and the results prove that this technology offers indeed extremely good performance. We have designed a Galois field multiplier with a systolic array structure to reduce interconnection overhead. We developed a new RTL model that allows us to easily describe and simulate circuits of any complexity, evaluating at the same time the performance and keeping into account technology constraints. We approach for the first time in the NML scenario the design of ME-NML circuits adopting the standard-cell method used in standard technologies and fulfill the design down to the physical level. The same circuit is designed also with NML technology based on magnetic fields and with a 28 nm low power CMOS bulk technology for comparison. The CMOS circuit is obtained through physical place&route with a commercial tool, providing, therefore, the most accurate comparison ever presented in literature. Power analysis shows that ME-NML circuits have a considerable advantage over both NML and state-of-the-art CMOS bulk technology. As a further by-product results clearly highlight which kind of architectures can better exploit the true potential of NML technology