Near-Memory Address Translation

Memory and logic integration on the same chip is becoming increasingly cost effective, creating the opportunity to offload data-intensive functionality to processing units placed inside memory chips. The introduction of memory-side processing units (MPUs) into conventional systems faces virtual memory as the first big showstopper: without efficient hardware support for address translation MPUs have highly limited applicability. Unfortunately, conventional translation mechanisms fall short of providing fast translations as contemporary memories exceed the reach of TLBs, making expensive page walks common. In this paper, we are the first to show that the historically important flexibility to map any virtual page to any page frame is unnecessary in today's servers. We find that while limiting the associativity of the virtual-to-physical mapping incurs no penalty, it can break the translate-then-fetch serialization if combined with careful data placement in the MPU's memory, allowing for translation and data fetch to proceed independently and in parallel. We propose the Distributed Inverted Page Table (DIPTA), a near-memory structure in which the smallest memory partition keeps the translation information for its data share, ensuring that the translation completes together with the data fetch. DIPTA completely eliminates the performance overhead of translation, achieving speedups of up to 3.81x and 2.13x over conventional translation using 4KB and 1GB pages respectively.Comment: 15 pages, 9 figure

Tip of the Iceberg: Low-Associativity Paging

Virtual address translation is a growing bottleneck for large data applications — such as machine learning and graph analytics — as each virtual address translation requires multiple, slow, memory accesses. TLBs attempt to solve this problem, but have limited coverage and cannot keep up with the rate at which virtual memory scales. This paper argues that a path forward is to reconsider the necessity of fully associative page translations, where any virtual page can map to any physical location. Reduced associativity, as in hashed page tables, can improve TLB coverage by reducing the number of bits needed to cache one translation. Unfortunately, reduced associativity is often implemented using techniques that cause usability problems that stem from associativity conflicts. We summarize a new hashing scheme, iceberg hashing, that is suitable for virtual memory, as it successfully addresses flaws in prior hashing schemes. This thesis describes how iceberg hashing can be implemented and used in a virtual memory system. Finally, the thesis presents a study and preliminary data using xv6, which indicates iceberg hashing can be configured such that associativity conflicts only manifest when memory is more than 95% full, and can be resolved using standard swapping techniques.Bachelor of Scienc

Efficient Data Access in Disruption Tolerant Networks Using Cooperative Caching with DRAMA

Disruption Tolerant Networks (DTNs) is characterized by low node density and unpredictable node mobility. The current research efforts in DTN focus on data forward in gand reduce absence of end-to-end path between source and destination, but only limited work has been done on providing efficient data accesses to mobile users. In this paper, we propose a greatly improved energy efficiency strategy named DRAMA aimed to improve storing and fast accessing of data in cache and also it supports cooperative caching in DTNs, which makes the sharing and coordination of cached data among multiple nodes and reduces data access delay. Our idea is to cache data at a set of nodes as network central locations (NCLs), which can be easily accessed by other nodes in the network. We propose an efficient scheme to select appropriate NCL based on probabilistic selection metric and coordinates multiple caching nodes to optimize the trade-off between data accessibility and caching overhead

A Virtual Tile Approach to Rastel-based Calculations of Large Digital Elevation Models in a Shared-Memory System

Grid digital elevation models (DEMs) are commonly used in hydrology to derive information related to topographically driven flow. Advances in technology for creating DEMs have increased their resolution and data size with the result that algorithms for processing them are frequently memory limited. This paper presents a new approach to the management of memory in the parallel solution of hydrologic terrain processing using a user-level virtual memory system for shared-memory multithreaded systems. The method includes tailored virtual memory management of raster-based calculations for datasets that are larger than available memory and a novel order-of-calculations approach to parallel hydrologic terrain analysis applications. The method is illustrated for the pit filling algorithm used first in most hydrologic terrain analysis workflows