Analog hardware security and hardware authentication

Hardware security and hardware authentication have become more and more important concerns in the manufacture of trusted integrated circuits. In this dissertation, a detailed study of hardware Trojans in analog circuits characterized by the presence of extra operating points or modes is presented. In a related study, a counterfeit countermeasure method based upon PUF authentication circuits is proposed for addressing the growing proliferation of counterfeit integrated circuits in the supply chain. Most concerns about hardware Trojans in semiconductor devices are based upon an implicit assumption that attackers will focus on embedding Trojans in digital hardware by making malicious modifications to the Boolean operation of a circuit. In stark contrast, hardware Trojans can be easily embedded in some of the most basic analog circuits. In this work, a particularly insidious class of analog hardware Trojans that require no architectural modifications, no area or power overhead, and prior to triggering, that leave no signatures in any power domains or delay paths is introduced. The Power/Architecture/Area/Signature Transparent (PAAST) characteristics help the Trojan “hide” and make them very difficult to detect with existing hardware Trojan detection methods. Cleverly hidden PAAST Trojans are nearly impossible to detect with the best simulation and verification tools, even if a full and accurate disclosure of the circuit schematic and layout is available. Aside from the work of the author of this dissertation and her classmates, the literature is void of discussions of PAAST analog hardware Trojans. In this work, examples of circuits showing the existence of PAAST analog hardware Trojans are given, the PAAST characteristics of these types of hardware Trojans are discussed, and heuristic detection methods that can help to detect these analog hardware Trojans are proposed. Another major and growing problem in the modern IC supply chain is the proliferation of counterfeit chips that are often characterized by different or inferior performance characteristics and reduced reliability when compared with authentic parts. A counterfeit countermeasure method is proposed that should lower the entry barrier for major suppliers of commercial off the shelf (COTS) parts to offer authenticated components to the military and other customers that have high component reliability requirements. The countermeasure is based upon a PUF authentication circuit that requires no area, pin, or power overhead, and causes no degradation of performance of existing and future COTS components

Low-cost, high-precision DAC design based on ordered element matching and verification against undesired operating points for analog circuits

Over the past 50 years, the integrated circuit (IC) industry has grown rapidly, following the famous ``Moore\u27s law. The process feature size keeps shrinking, whereby the performance of digital circuits is constantly enhanced and their cost constantly decreases. However, with the system integration and the development of system on chip (SoC), nearly all of today\u27s ICs contain analog/mixed-Signal circuits. Although a mixed-signal SoC is primarily digital, the analog circuit design and verification consume most of the resources, and the dominant source of IC breakdowns is attributable to the analog circuits. One important reason for the high cost and risk of breakdowns of analog circuits is that the technology advancement does not benefit many analog and mixed-signal circuits, and in fact imposes higher requirements on their performance. With process scaling, many important parameters of integrated circuit components degrade, which cause a drop in many key aspects of performance of analog circuits. Many analog circuits rely on matched circuit components (transistors, resistors, or capacitors) to achieve the required linearity performance; examples are amplifiers, digital-to-analog converters (DACs), etc. However, shrinking of the feature sizes increases the circuit components mismatch, thereby making it more difficult to maintain circuit accuracy. Therefore, to reduce the cost of analog circuit design, designers should propose new structures whose key performance can be improved by the technology scaling. In this dissertation, we propose a low-cost, high-precision DAC structure based on ordered element matching (OEM) theory. High matching accuracy can be achieved by applying OEM calibration to the resistors in unary weighted segments and calibrating the gain error between different segments by calibration DAC (CalDAC). As a design example to verify the proposed structure, a high-precision DAC is designed in a 130 nm Global Foundry (GF) CMOS process. The 130 nm GF process features high-density digital circuits and is a typical process which is constantly enhanced by the scaling of device dimensions and voltage supply; implementation of a high-precision DAC in such process is important to decreasing the costs of high-precision DAC designs. As a result, our proposed DAC structure is demonstrated to be able to significantly lower the cost of high-precision DAC design. Another reason for the high cost and risk of breakdowns of analog circuits arises from the complexity of analog circuit working states. Most digital circuits serve as logic functions, so that digital transistors work in only two states, either low or high. In contrast, analog circuits have much more complicated functions; they may work in multiple operating points, since various feedback approaches are applied in analog circuits to enhance their performance. Circuits with undetected operating points can be devastating, particularly when they are employed in critical applications such as automotive, health care, and military products. However, since the existing circuit simulators provide only a single operating point, recognizing the existence of undesired operating points depends largely on the experiences of designers. In some circuits, even the most experienced designers may not be aware that a circuit they designed has undesired operating points, which often go undetected in the standard simulations in the design process. To identify undesired operating points in an analog circuit and reduce its risk of breakdowns, a systematic verification method against undesired operating points in analog circuits is proposed in this dissertation. Unlike traditional methods of finding all operating points, this method targets only searches for voltage intervals containing undesired operating points. To achieve this, our method first converts the circuit into a corresponding graph and locates the break point to break all the positive feedback loops (PFLs). For one dimensional verification, divide and contraction algorithms could be applied to identify undesired operating points. Two dimensional vector field methods are used to solve the two dimensional verifications. Based on the proposed verification methods against undesired operating points, an EDA tool called ``ITV is developed to identify undesired operating points in analog and mixed-signal circuits. Simulation results show ITV to be effective and efficient in identifying undesired operating points in a class of commonly used benchmark circuits that includes bias generators, voltage references, temperature sensors, and op-amp circuits

Design and verification approaches for reliability and functional safety of analog integrated circuits

New breakthroughs in semiconductor design have enabled a rapid integration of semiconductor chips into systems that affect all aspects of the society. Examples of emerging systems include spacecraft, Internet of Things (IoT), intelligent automotive, and bio-implantable devices. Many of these systems are mission-critical or safety-critical, meaning that failure or malfunction may lead to severe economical losses, environmental damages or risks to human lives. In addition to performances improvement, the reliability and functional safety of the underlying integrated circuit (IC) have attracted more and more attention and have posed grand challenges for semiconductor industries. This dissertation introduces an approach for high performance voltage reference design and investigates two subjects that improve the reliability and functional safety of analog circuits. The first part of this dissertation studies design strategies of a low temperature-coefficient voltage reference generator, which is a fundamental building block and determines the maximum achievable performance of almost all analog/mixed-signal systems. The proposed method is targeted at extracting a physical quantity of the silicon bandgap, and has the potential of designing a voltage reference that has qualitatively better temperature dependence. An implementation of the proposed approach in GlobalFoundries 130nm process shows that the design can achieve temperature coefficients as low as 0.7ppm/°C over a temperature range of -40°C to 125°C over all process corners. The second part of this dissertation focuses on multi-states verification of analog circuits. The multiple DC equilibrium points or multi-states problem traces back to IC design. It is a well-known problem in many basic self-stabilized analog circuits because of the existence of positive feedback loops (PFLs). This work proposes systematic and automatic approaches for locating all PFLs to identify circuits vulnerable to undesired equilibrium states and methods for automatically identifying break-points to break all PFLs in the vulnerable circuits. The proposed methods make it possible to efficiently identify a circuit’s vulnerability to undesired operating points by considering circuit topology only, without the need for finding all possible solutions to a set of simultaneous nonlinear equations which is an open problem with no solution. Moreover, the automatic break-points identification enables easy use of homotopy analysis to guarantee absence of undesired states. The third part of this dissertation focuses on fault coverage simulation of analog circuits. This work describe two methods, one is to reduce the fault coverage estimation time and the other is to improve the fault coverage for analog circuits. The first method incorporates graph theory and sensitivity analysis and leads to dramatic reduction in fault coverage simulation time by 10’s of times for a moderately sized analog circuit. The second method discusses a systematic test-points selection technique to improve the analog fault coverage with simple DC tests and a concurrent sampling technique for monitoring these points. This work could be applied to manufacturing testing or for real-time fault detection