Efficient Quantum Circuits for Non-Qubit Quantum Error-Correcting Codes

We present two methods for the construction of quantum circuits for quantum error-correcting codes (QECC). The underlying quantum systems are tensor products of subsystems (qudits) of equal dimension which is a prime power. For a QECC encoding k qudits into n qudits, the resulting quantum circuit has O(n(n-k)) gates. The running time of the classical algorithm to compute the quantum circuit is O(n(n-k)^2).Comment: 18 pages, submitted to special issue of IJFC

Short random circuits define good quantum error correcting codes

We study the encoding complexity for quantum error correcting codes with large rate and distance. We prove that random Clifford circuits with $O(n \log^2 n)$ gates can be used to encode $k$ qubits in $n$ qubits with a distance $d$ provided $\frac{k}{n} < 1 - \frac{d}{n} \log_2 3 - h(\frac{d}{n})$. In addition, we prove that such circuits typically have a depth of $O( \log^3 n)$.Comment: 5 page

Comparing the Overhead of Topological and Concatenated Quantum Error Correction

This work compares the overhead of quantum error correction with concatenated and topological quantum error-correcting codes. To perform a numerical analysis, we use the Quantum Resource Estimator Toolbox (QuRE) that we recently developed. We use QuRE to estimate the number of qubits, quantum gates, and amount of time needed to factor a 1024-bit number on several candidate quantum technologies that differ in their clock speed and reliability. We make several interesting observations. First, topological quantum error correction requires fewer resources when physical gate error rates are high, white concatenated codes have smaller overhead for physical gate error rates below approximately 10E-7. Consequently, we show that different error-correcting codes should be chosen for two of the studied physical quantum technologies - ion traps and superconducting qubits. Second, we observe that the composition of the elementary gate types occurring in a typical logical circuit, a fault-tolerant circuit protected by the surface code, and a fault-tolerant circuit protected by a concatenated code all differ. This also suggests that choosing the most appropriate error correction technique depends on the ability of the future technology to perform specific gates efficiently