Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder

In this article, we present an efficient implementation for the current-mode radix-2 Signed-Digit Full Adder (SDFA). It is based on negative-differential-resistance (NDR) MOS structures. Simulations have been carried out using a 0.13-mu m SOI CMOS technology. Since it uses Dynamic Current-Mode Logic (DyCML) comparators and features a dual-rail structure, the NDR-MOS SDFA shows a higher speed and lower power consumption than previously reported implementations. It can be used to design an N-bit constant-time adder with a 227-ps delay and a power consumption of 33 mu W per digit at 2-GHz clock frequency. The 64-bit version exhibits higher performance than a state-of-the-art fully optimized 64-bit carry-select adder implemented on the same technology