Efficient Low-Cost Sharing Design of Fast 1-D Inverse Integer Transform Algorithms for H.264/AVC and VC-1

In this letter, the fast one-dimensional (1-D) algorithms and their sharing design for 1-D inverse integer transforms of H.264/AVC and VC-1 are proposed by using the matrix decompositions with the sparse matrices and the matrix offset computations. The computational complexities of the proposed fast 1-D 4 x 4 and 8 x 8 inverse integer transforms for H.264/AVC are the same as those of the previous fast methods. Then the shift operations of the proposed fast 1-D inverse integer transform for VC-1 are equivalent to those of the previous fast method. For playback environments, the video decoder can support the multiple modes, which include H.264/AVC and VC-1 video standards. The proposed hardware sharing architecture requires lower hardware cost than the individual and separate design for the VLSI realization

A Systematic Hardware Sharing Method for Unified Architecture Design of H.264 Transforms

Multitransform techniques have been widely used in modern video coding and have better compression efficiency than the single transform technique that is used conventionally. However, every transform needs a corresponding hardware implementation, which results in a high hardware cost for multiple transforms. A novel method that includes a five-step operation sharing synthesis and architecture-unification techniques is proposed to systematically share the hardware and reduce the cost of multitransform coding. In order to demonstrate the effectiveness of the method, a unified architecture is designed using the method for all of the six transforms involved in the H.264 video codec: 2D 4 × 4 forward and inverse integer transforms, 2D 4 × 4 and 2 × 2 Hadamard transforms, and 1D 8 × 8 forward and inverse integer transforms. Firstly, the six H.264 transform architectures are designed at a low cost using the proposed five-step operation sharing synthesis technique. Secondly, the proposed architecture-unification technique further unifies these six transform architectures into a low cost hardware-unified architecture. The unified architecture requires only 28 adders, 16 subtractors, 40 shifters, and a proposed mux-based routing network, and the gate count is only 16308. The unified architecture processes 8 pixels/clock-cycle, up to 275 MHz, which is equal to 707 Full-HD 1080 p frames/second