Efficient Latch Optimization Using Exclusive Sets

Controller circuits synthesized from high-level languages often have many more latches than the minimum, with a resulting sparse reachable state space that has a particular structure. We propose an algorithm that exploits this structure to remove latches. The reachable state set (RSS) is much easier to compute for the new, smaller circuit and can be used to efficiently compute the RSS of the original. Thus we provide a method for obtaining the RSS, and two different initial implementations from which to begin logic optimization. 1 Introduction The computation of the reachable state set (RSS) of a sequential circuit is important for verification, logic optimization and test generation. The RSS computation is typically done incrementally, by looping over a computation of the next states as the image of the current states by a vector of Boolean functions [3]. When BDD-based algorithms are used, the variables are the latches and the circuit inputs. Therefore, the number of latch..