Modeling of CMOS devices and circuits on flexible ultrathin chips

The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications. However, simulation and prediction of changes in response of device/circuit due to bending induced stress remains a challenge as of lack of suitable compact models. This makes circuit designing for bendable electronics a difficult task. This paper presents advances in this direction, through compressive and tensile stress studies on transistors and simple circuits such as inverters with different channel lengths and orientations of transistors on ultrathin chips. Different designs of devices and circuits in a standard CMOS 0.18-μm technology were fabricated in two separated chips. The two fabricated chips were thinned down to 20 μm using standard dicing-before-grinding technique steps followed by post-CMOS processing to obtain sufficient bendability (20-mm bending radius, or 0.05% nominal strain). Electrical characterization was performed by packaging the thinned chip on a flexible substrate. Experimental results show change of carrier mobilities in respective transistors, and switching threshold voltage of the inverters during different bending conditions (maximum percentage change of 2% for compressive and 4% for tensile stress). To simulate these changes, a compact model, which is a combination of mathematical equations and extracted parameters from BSIM4, has been developed in Verilog-A and compiled into Cadence Virtuoso environment. The proposed model predicts the mobility variations and threshold voltage in compressive and tensile bending stress conditions and orientations, and shows an agreement with the experimental measurements (1% for compressive and 0.6% for tensile stress mismatch)

Device Modelling of Silicon Based High-Performance Flexible Electronics

The area of flexible electronics is rapidly expanding and evolving. With applications requiring high speed and performance, ultra-thin silicon-based electronics has shown its prominence. However, the change in device response upon bending is a major concern. In absence of suitable analytical and design tool friendly model, the behavior under bent condition is hard to predict. This poses challenges to circuit designer working in the bendable electronics field, in laying out a design that can give a precise response in a stressed condition. This paper presents advances in this direction and investigates the effect of compressive and tensile stress on the performance of NMOS and PMOS transistor and a touch sensor comprising a transistor and piezoelectric capacitor

Smart Sensor Networks For Sensor-Neural Interface

One in every fifty Americans suffers from paralysis, and approximately 23% of paralysis cases are caused by spinal cord injury. To help the spinal cord injured gain functionality of their paralyzed or lost body parts, a sensor-neural-actuator system is commonly used. The system includes: 1) sensor nodes, 2) a central control unit, 3) the neural-computer interface and 4) actuators. This thesis focuses on a sensor-neural interface and presents the research related to circuits for the sensor-neural interface. In Chapter 2, three sensor designs are discussed, including a compressive sampling image sensor, an optical force sensor and a passive scattering force sensor. Chapter 3 discusses the design of the analog front-end circuit for the wireless sensor network system. A low-noise low-power analog front-end circuit in 0.5μm CMOS technology, a 12-bit 1MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18μm CMOS process and a 6-bit asynchronous level-crossing ADC realized in 0.18μm CMOS process are presented. Chapter 4 shows the design of a low-power impulse-radio ultra-wide-band (IR-UWB) transceiver (TRx) that operates at a data rate of up to 10Mbps, with a power consumption of 4.9pJ/bit transmitted for the transmitter and 1.12nJ/bit received for the receiver. In Chapter 5, a wireless fully event-driven electrogoniometer is presented. The electrogoniometer is implemented using a pair of ultra-wide band (UWB) wireless smart sensor nodes interfacing with low power 3-axis accelerometers. The two smart sensor nodes are configured into a master node and a slave node, respectively. An experimental scenario data analysis shows higher than 90% reduction of the total data throughput using the proposed fully event-driven electrogoniometer to measure joint angle movements when compared with a synchronous Nyquist-rate sampling system. The main contribution of this thesis includes: 1) the sensor designs that emphasize power efficiency and data throughput efficiency; 2) the fully event-driven wireless sensor network system design that minimizes data throughput and optimizes power consumption

Image compression and energy harvesting for energy constrained sensors

Title from PDF of title page, viewed on June 21, 2013Dissertation advisor: Walter D. Leon-SalasVitaIncludes bibliographic references (pages 176-[187])Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2013The advances in complementary metal-oxide-semiconductor (CMOS) technology have led to the integration of all components of electronic system into a single integrated circuit. Ultra-low power circuit techniques have reduced the power consumption of circuits. Moreover, solar cells with improved efficiency can be integrated on chip to harvest energy from sunlight. As a result of all the above, a new class of miniaturized electronic systems known as self-powered system on a chip has emerged. There is an increasing research interest in the area of self-powered devices which provide cost-effective solutions especially when these devices are used in the areas that changing or replacing batteries is too costly. Therefore, image compression and energy harvesting are studied in this dissertation. The integration of energy harvesting, image compression, and an image sensor on the same chip provides the energy source to charge a battery, reduces the data rate, and improves the performance of wireless image sensors. Integrated circuits of image compression, solar energy harvesting, and image sensors are studied, designed, and analyzed in this work. In this dissertation, a hybrid image sensor that can perform the tasks of sensing and energy harvesting is presented. Photodiodes of hybrid image sensor can be programmed as image sensors or energy harvesting cells. The hybrid image sensor can harvest energy in between frames, in sleep mode, and even when it is taking images. When sensing images and harvesting energy are both needed at the same time, some pixels have to work as sensing pixels, and the others have to work as solar cells. Since some pixels are devoted to harvest energy, the resolution of the image will be reduced. To preserve the resolution or to keep the fair resolution when a lot of energy collection is needed, image reconstruction algorithms and compressive sensing theory provide solutions to achieve a good image quality. On the other hand, when the battery has enough charge, image compression comes into the picture. Multiresolution decomposition image compression provides a way to compress image data in order to reduce the energy need from data transmission. The solution provided in this dissertation not only harvests energy but also saves energy resulting long lasting wireless sensors. The problem was first studied at the system level to identify the best system-level configuration which was then implemented on silicon. As a proof of concept, a 32 x 32 array of hybrid image sensor, a 32 x 32 array of image sensor with multiresolution decomposition compression, and a compressive sensing converter have been designed and fabricated in a standard 0.5 [micrometer] CMOS process. Printed circuit broads also have been designed to test and verify the proposed and fabricated chips. VHDL and Matlab codes were written to generate the proper signals to control, and read out data from chips. Image processing and recovery were carried out in Matlab. DC-DC converters were designed to boost the inherently low voltage output of the photodiodes. The DC-DC converter has also been improved to increase the efficiency of power transformation.Introduction -- Hybrid imager system and circuit design -- Hybrid imager energy harvesting and image acquisition results and discussion -- Detailed description and mathematical analysis for a circuit of energy harvesting using on-chip solar cells -- Multiresolution decomposition for lossless and near-lossless compression -- An incremental [sigma-delta] converter for compressive sensing -- Detailed description of a sigma-delta random demodulator converter architecture for compressive sensing applications -- Conclusion -- Appendix A. Chip pin-out -- Appendix B. Schematics -- Appendix C. Pictures of custom PC

Low Power Autonomous Microsystem for Oil Well Logging Applications

Downhole environmental monitoring can provide significant benefits to the petroleum industry. The rapid development of semiconductor technology enables autonomous sensing microsystems to operate at extreme environments. By injecting these microsystems into the boreholes and retrieving them after deployment, the geophysical conditions in the area of interest can be obtained. Challenges include high temperature, high pressure, miniaturized system size and packaging. This dissertation describes three generations of the environmental logging microsystem (ELM) for downhole geophysical logging applications. The first generation of the microsystem, ELM1.0, is designed for temperature logging in downhole environments. Each system consists of a power management circuit, a microcontroller with an integrated temperature sensor, and optical indicators. The system electronics are integrated on a flexible printed circuit board and packaged in a steel shell. The ELM1.0 has a packaged size of 8.9×8.9×6.85 mm3. It was tested at up to 125°C, 50 MPa in high salinity condition. The second generation (ELM2.0 & ELM2.1) is upgraded from ELM1.0 by adding a micromachined capacitive pressure sensor for pressure sensing up to 50 MPa. The ELM2.0 & ELM2.1 systems are packaged in steel shells filled with transparent polymer for pressure transfer. The packaged systems have a dimension of 9.5×9.5×6.5 mm3. The third generation (ELM3.0) is upgraded from ELM2.0 with a power switch and a low-cost polyimide pressure sensor for coarse pressure measurement up to 50 MPa. Both ELM2.0 and ELM3.0 systems were successfully tested at up to 125°C, 50 MPa in corrosive environments using laboratory instruments, and in a brine well at a depth up to 1235 m. A progressive polynomial calibration method was used for interpretation of the pressure sensor data from these tests. In addition, a high power micromachined RF switch for radio transceiver applications was designed, fabricated and tested. The RF switch can potentially be used to establish antenna networks for RF communication in the ELM. The switch consists of a bridge structure for electrostatic actuation and capacitive contact. The switch was fabricated with a 7-mask process. The fabricated device showed limited RF performance because of challenges related to the control of residual stress in suspended elements.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138647/1/sui_1.pd

Ultra-thin and flexible CMOS technology: ISFET-based microsystem for biomedical applications

A new paradigm of silicon technology is the ultra-thin chip (UTC) technology and the emerging applications. Very thin integrated circuits (ICs) with through-silicon vias (TSVs) will allow the stacking and interconnection of multiple dies in a compact format allowing a migration towards three-dimensional ICs (3D-ICs). Also, extremely thin and therefore mechanically bendable silicon chips in conjunction with the emerging thin-film and organic semiconductor technologies will enhance the performance and functionality of large-area flexible electronic systems. However, UTC technology requires special attention related to the circuit design, fabrication, dicing and handling of ultra-thin chips as they have different physical properties compared to their bulky counterparts. Also, transistors and other active devices on UTCs experiencing variable bending stresses will suffer from the piezoresistive effect of silicon substrate which results in a shift of their operating point and therefore, an additional aspect should be considered during circuit design. This thesis tries to address some of these challenges related to UTC technology by focusing initially on modelling of transistors on mechanically bendable Si-UTCs. The developed behavioural models are a combination of mathematical equations and extracted parameters from BSIM4 and BSIM6 modified by a set of equations describing the bending-induced stresses on silicon. The transistor models are written in Verilog-A and compiled in Cadence Virtuoso environment where they were simulated at different bending conditions. To complement this, the verification of these models through experimental results is also presented. Two chips were designed using a 180 nm CMOS technology. The first chip includes nMOS and pMOS transistors with fixed channel width and two different channel lengths and two different channel orientations (0° and 90°) with respect to the wafer crystal orientation. The second chip includes inverter logic gates with different transistor sizes and orientations, as in the previous chip. Both chips were thinned down to ∼20m using dicing-before-grinding (DBG) prior to electrical characterisation at different bending conditions. Furthermore, this thesis presents the first reported fully integrated CMOS-based ISFET microsystem on UTC technology. The design of the integrated CMOS-based ISFET chip with 512 integrated on-chip ISFET sensors along with their read-out and digitisation scheme is presented. The integrated circuits (ICs) are thinned down to ∼30m and the bulky, as well as thinned ICs, are electrically and electrochemically characterised. Also, the thesis presents the first reported mechanically bendable CMOS-based ISFET device demonstrating that mechanical deformation of the die can result in drift compensation through the exploitation of the piezoresistive nature of silicon. Finally, this thesis presents the studies towards the development of on-chip reference electrodes and biodegradable and ultra-thin biosensors for the detection of neurotransmitters such as dopamine and serotonin

Energy harvesting technologies and devices from vehicular transit and natural sources on roads for a sustainable transport: state-of-the-art analysis and commercial solutions

The roads we travel daily are exposed to several energy sources (mechanical load, solar radiation, heat, air movement, etc.), which can be exploited to make common systems and apparatus for roadways (i.e., lighting, video surveillance, and traffic monitoring systems) energetically autonomous. For decades, research groups have developed many technologies able to scavenge energy from the said sources related to roadways: electromagnetism, piezoelectric and triboelectric harvesters for the cars’ stress and vibrations, photovoltaic modules for sunlight, thermoelectric solutions and pyroelectric materials for heat and wind turbines optimized for low-speed winds, such as the ones produced by moving vehicles. Thus, this paper explores the existing technologies for scavenging energy from sources available on roadways, both natural and related to vehicular transit. At first, to contextualize them within the application scenario, the available energy sources and transduction mechanisms were identified and described, arguing the main requirements that must be considered for developing harvesters applicable on roadways. Afterward, an overview of energy harvesting solutions presented in the scientific literature to recover energy from roadways is introduced, classifying them according to the transduction method (i.e., piezoelectric, triboelectric, electromagnetic, photovoltaic, etc.) and proposed system architecture. Later, a survey of commercial systems available on the market for scavenging energy from roadways is introduced, focusing on their architecture, performance, and installation methods. Lastly, comparative analyses are offered for each device category (i.e., scientific works and commercial products), providing insights to identify the most promising solutions and technologies for developing future self-sustainable smart roads

Learning-Based Hardware Design for Data Acquisition Systems

This multidisciplinary research work aims to investigate the optimized information extraction from signals or data volumes and to develop tailored hardware implementations that trade-off the complexity of data acquisition with that of data processing, conceptually allowing radically new device designs. The mathematical results in classical Compressive Sampling (CS) support the paradigm of Analog-to-Information Conversion (AIC) as a replacement for conventional ADC technologies. The AICs simultaneously perform data acquisition and compression, seeking to directly sample signals for achieving specific tasks as opposed to acquiring a full signal only at the Nyquist rate to throw most of it away via compression. Our contention is that in order for CS to live up its name, both theory and practice must leverage concepts from learning. This work demonstrates our contention in hardware prototypes, with key trade-offs, for two different fields of application as edge and big-data computing. In the framework of edge-data computing, such as wearable and implantable ecosystems, the power budget is defined by the battery capacity, which generally limits the device performance and usability. This is more evident in very challenging field, such as medical monitoring, where high performance requirements are necessary for the device to process the information with high accuracy. Furthermore, in applications like implantable medical monitoring, the system performances have to merge the small area as well as the low-power requirements, in order to facilitate the implant bio-compatibility, avoiding the rejection from the human body. Based on our new mathematical foundations, we built different prototypes to get a neural signal acquisition chip that not only rigorously trades off its area, energy consumption, and the quality of its signal output, but also significantly outperforms the state-of-the-art in all aspects. In the framework of big-data and high-performance computation, such as in high-end servers application, the RF circuits meant to transmit data from chip-to-chip or chip-to-memory are defined by low power requirements, since the heat generated by the integrated circuits is partially distributed by the chip package. Hence, the overall system power budget is defined by its affordable cooling capacity. For this reason, application specific architectures and innovative techniques are used for low-power implementation. In this work, we have developed a single-ended multi-lane receiver for high speed I/O link in servers application. The receiver operates at 7 Gbps by learning inter-symbol interference and electromagnetic coupling noise in chip-to-chip communication systems. A learning-based approach allows a versatile receiver circuit which not only copes with large channel attenuation but also implements novel crosstalk reduction techniques, to allow single-ended multiple lines transmission, without sacrificing its overall bandwidth for a given area within the interconnect's data-path

Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants

Implantable systems are nowadays being used to interface the human brain with external devices, in order to understand and potentially treat neurological disorders. The most predominant design constraints are the system’s area and power. In this paper, we implement and combine advanced compressive sampling algorithms to reduce the power requirements of wireless telemetry. Moreover, we apply variable compression, to dynamically modify the device performance, based on the actual signal need. This paper presents an area-efficient adaptive system for wireless implantable devices, which dynamically reduces the power requirements yielding compression rates from 8× to 64×, with a high reconstruction performance, as qualitatively demonstrated on a human data set. Two different versions of the encoder have been designed and tested, one with and the second without the adaptive compression, requiring an area of 230×235 μm and 200 × 190 μm, respectively, while consuming only 0.47 μW at 0.8 V. The system is powered by a 4-coil inductive link with measured power transmission efficiency of 36%, while the distance between the external and internal coils is 10 mm. Wireless data communication is established by an OOK modulated narrowband and an IR-UWB transmitter, while consuming 124.2 pJ/bit and 45.2 pJ/pulse, respectively