HTML5 Canvas software libraries

Verkkosivujen tekninen kehitys on siirtymässä vahvasti ilman selainliitännäisiä toimiviin sivustoihin. HTML5-standardin mukana kehitetty Canvas-elementti tarjoaa ne graafiset ominaisuudet, jotka oli aiemmin mahdollista toteuttaa vain selainliitännäisten avulla. Tässä tutkimuksessa tarkastellaan HTML5 Canvas-elementin ohjelmointiin tarkoitettuja ohjelmointikirjastoja. Tavoitteena on löytää tehokas, kaupalliseen käyttöön soveltuva kirjasto, joka täyttää tutkimuksessa asetetut vaatimukset. Tutkimuksessa tarkasteltiin 42 ohjelmointikirjastoa, jotka on julkaistu kaupallisen käytön sallivalla avoimen lähdekoodin lisenssillä. Kirjastoista seitsemän täytti tutkimuksessa asetetut, teknisiä ominaisuuksia ja kehitysprojektin laatua koskevat vaatimukset. Näille kirjastoille tehtiin suoritustehokkuutta ja muistinkäyttöä mittaavat testit. Teknisessä testauksessa ohjelmointikirjastoilla koostettiin vektori- ja bittikarttagrafiikkaa piirtävät vertailuohjelmat. Testiohjelmilla mitattiin ruudunpäivitysnopeus sekä varatun muistin määrä. Testit suoritettiin sekä pöytätietokoneella että mobiiliympäristössä varioiden ruudulle piirrettävän grafiikan määrää. Tutkimuksessa saadut tulokset osoittavat, että HTML5 Canvas-ohjelmistokirjastoilla on selviä eroja suoritustehokkuudessa sekä muistinkäytössä. Tutkituista ohjelmointikirjastoista parhaiksi valikoituivat Easel.js ja Pixi.js.The development of websites is heading towards plugin-free architecture. HTML5 specification introduced a new Canvas element that includes graphical properties which could previously only be achived by using browser add-ons. This thesis examines software libraries that are geared towards development of HTML5 Canvas applications. The aim of this study is to identify a software library that is efficient, suitable for commercial use and meets the other requirements presented in this study. This study analysed 42 software libraries, which were published using open source license that enables commercial use. Seven libraries met the requirements of this study regarding technical features and qualifications that were required from the development project of the software library. These seven libraries were selected for performance and memory usage testing. The performance tests were done using sample programs that drew vector and bitmap graphics on HTML5 Canvas. The sample programs were measured for redraw speed of the graphics and memory usage. These tests were carried out on desktop and mobile environments with various number of graphical elements. In conclusion results of the study showed that there are clear differences between HTML5 Canvas libraries regarding performance and memory usage. Out of all libraries Easel.js and Pixi.js libraries were selected as the best HTML5 Canvas libraries

Dynamic parallelization of javascript applications using an ultra-lightweight speculation mechanism

Abstrac

Architectural Enhancements for Data Transport in Datacenter Systems

Datacenter systems run myriad applications, which frequently communicate with each other and/or Input/Output (I/O) devices—including network adapters, storage devices, and accelerators. Due to the growing speed of I/O devices and the emergence of microservice-based programming models, the I/O software stacks have become a critical factor in end-to-end communication performance. As such, I/O software stacks have been evolving rapidly in recent years. Datacenters rely on fast, efficient “Software Data Planes”, which orchestrate data transfer between applications and I/O devices. The goal of this dissertation is to enhance the performance, efficiency, and scalability of software data planes by diagnosing their existing issues and addressing them through hardware-software solutions. In the first step, I characterize challenges of modern software data planes, which bypass the operating system kernel to avoid associated overheads. Since traditional interrupts and system calls cannot be delivered to user code without kernel assistance, kernel-bypass data planes use spinning cores on I/O queues to identify work/data arrival. Spin-polling obviously wastes CPU cycles on checking empty queues; however, I show that it entails even more drawbacks: (1) Full-tilt spinning cores perform more (useless) polling work when there is less work pending in the queues. (2) Spin-polling scales poorly with the number of polled queues due to processor cache capacity constraints, especially when traffic is unbalanced. (3) Spin-polling also scales poorly with the number of cores due to the overhead of polling and operation rate limits. (4) Whereas shared queues can mitigate load imbalance and head-of-line blocking, synchronization overheads of spinning on them limit their potential benefits. Next, I propose a notification accelerator, dubbed HyperPlane, which replaces spin-polling in software data planes. Design principles of HyperPlane are: (1) not iterating on empty I/O queues to find work/data in ready ones, (2) blocking/halting when all queues are empty rather than spinning fruitlessly, and (3) allowing multiple cores to efficiently monitor a shared set of queues. These principles lead to queue scalability, work proportionality, and enjoying theoretical merits of shared queues. HyperPlane is realized with a programming model front-end and a hardware microarchitecture back-end. Evaluation of HyperPlane shows its significant advantage in terms of throughput, average/tail latency, and energy efficiency over a state-of-the-art spin-polling-based software data plane, with very small power and area overheads. Finally, I focus on the data transfer aspect in software data planes. Cache misses incurred by accessing I/O data are a major bottleneck in software data planes. Despite considerable efforts put into delivering I/O data directly to the last-level cache, some access latency is still exposed. Cores cannot prefetch such data to nearer caches in today's systems because of the complex access pattern of data buffers and the lack of an appropriate notification mechanism that can trigger the prefetch operations. As such, I propose HyperData, a data transfer accelerator based on targeted prefetching. HyperData prefetches exact (rather than predicted) data buffers (or a required subset to avoid cache pollution) to the L1 cache of the consumer core at the right time. Prefetching can be done for both core-peripheral and core-core communications. HyperData's prefetcher is programmable and supports various queue formats—namely, direct (regular), indirect (Virtio), and multi-consumer queues. I show that with a minor overhead, HyperData effectively hides data access latency in software data planes, thereby improving both application- and system-level performance and efficiency.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/169826/1/hosseing_1.pd