2 research outputs found
Low power high speed and high accuracy design methodologies for pipeline Analog-to-Digital converters
Different aspects of power optimization of a high-speed, high-accuracy pipeline Analog-to-Digital Converters (ADCs) are considered to satisfy the current and future needs of portable communication devices. First power optimized design strategies for the amplifiers are introduced. Closed form expressions of power w.r.t settling requirements are presented to facilitate a fair comparison and selection of the amplifier structure. Next a new low offset dynamic comparator has been designed. Simulation based sensitivity analysis is performed to demonstrate the robustness of the new comparator with respect to stray capacitances, common mode voltage errors and timing errors. With simplified amplifier power model along with the use of dynamic comparators, a method to optimize the power consumption of a pipeline ADC with kT/C noise constraint is also developed. The total power dependence on capacitor scaling and stage resolution is investigated for a near-optimal solution.;After considering the power requirements of a pipeline ADC, design and statistical modeling of over-range protection requirements is investigated. Closed form statistical expressions for the over-range requirements are developed to assist in the allocation of the error budgets to different pipeline blocks. A new over-range protection algorithm is also developed that relaxes the amplifier design and power requirements.;Finally, two new CMOS Schmitt trigger designs are proposed which can be used as clock inputs for the pipeline ADC. In the new designs, sizing of the feedback inverters is used for independent trip point control. The new designs have also a modest reduction in sensitivity to process variations along with immunity to the kick-back noise without the addition of path delay
Recommended from our members
Low-voltage data converters
With the growing demand for portable/consumer electronics, such as digital
audio/video (AV), the downscaling of device dimensions, which enables the
integration of an increasing number of transistors in a single chip, is mandatory.
This trend also continuously pushes the power supply voltage down to reduce the
power consumption and improve the reliability of gate dielectrics. While the
reduction of power supply voltage is of great benefit to the essential digital blocks
in the system like data storage and digital signal processing, it makes it hard to
operate the important and indispensable analog building blocks such as data
converters and drivers.
In this thesis, the novel structures for the low-voltage digital-to-analog
converter (DAC) and analog-to-digital converter (ADC) are presented. The
research contributions of this work include (1) a sub-1V audio [delta sigma] DAC with one
opamp used per channel to implement D/A conversion, 1st-order FIR and 2ndorder
IIR filtering, as well as power amplification for the headphone, (2) a sub-1V
pipelined ADC with the novel MDAC based on a low-voltage track-and-hold
amplifier. Two prototypes, one is a 0.8V, 88dB dual-channel audio [delta sigma] DAC with
headphone driver, the other one is a 0.8V, 10-bit, 10MS/s pipelined ADC were
fabricated to verify the functionality of the proposed structures in standard CMOS
processes