An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

High-speed equalization and transmission in electrical interconnections

The relentless growth of data traffic and increasing digital signal processing capabilities of integrated circuits (IC) are demanding ever faster chip-to-chip / chip-to-module serial electrical interconnects. As data rates increase, the signal quality after transmission over printed circuit board (PCB) interconnections is severely impaired. Frequency-dependent loss and crosstalk noise lead to a reduced eye opening, a reduced signal-to-noise ratio and an increased inter-symbol interference (ISI). This, in turn, requires the use of improved signal processing or PCB materials, in order to overcome the bandwidth (BW) limitations and to improve signal integrity. By applying an optimal combination of equalizer and receiver electronics together with BW-efficient modulation schemes, the transmission rate over serial electrical interconnections can be pushed further. At the start of this research, most industrial backplane connectors, meeting the IEEE and OIF specifications such as manufactured by e.g. FCI or TE connectivity, had operational capabilities of up to 25 Gb/s. This research was mainly performed under the IWT ShortTrack project. The goal of this research was to increase the transmission speed over electrical backplanes up to 100 Gb/s per channel for next-generation telecom systems and data centers. This requirement greatly surpassed the state-ofthe-art reported in previous publications, considering e.g. 25 Gb/s duobinary and 42.8 Gb/s PAM-4 transmission over a low-loss Megtron 6 electrical backplane using off-line processing. The successful implementation of the integrated transmitter (TX) and receiver (RX) (1) , clearly shows the feasibility of single lane interconnections beyond 80 Gb/s and opens the potential of realizing industrial 100 Gb/s links using a recent IC technology process. Besides the advancement of the state-of-the-art in the field of high-speed transceivers and backplane transmission systems, which led to several academic publications, the output of this work also attracts a lot of attention from the industry, showing the potential to commercialize the developed chipset and technologies used in this research for various applications: not only in high-speed electrical transmission links, but also in high-speed opto-electronic communications such as access, active optical cables and optical backplanes. In this dissertation, the background of this research, an overview of this work and the thesis organization are illustrated in Chapter 1. In Chapter 2, a system level analysis is presented, showing that the channel losses are limiting the transmission speed over backplanes. In order to enhance the serial data rate over backplanes and to eliminate the signal degradation, several technologies are discussed, such as signal equalization and modulation techniques. First, a prototype backplane channel, from project partner FCI, implemented with improved backplane connectors is characterized. Second, an integrated transversal filter as a feed-forward equalizer (FFE) is selected to perform the signal equalization, based on a comprehensive consideration of the backplane channel performance, equalization capabilities, implementation complexity and overall power consumption. NRZ, duobinary and PAM-4 are the three most common modulation schemes for ultra-high speed electrical backplane communication. After a system-level simulation and comparison, the duobinary format is selected due to its high BW efficiency and reasonable circuit complexity. Last, different IC technology processes are compared and the ST microelectronics BiCMOS9MW process (featuring a fT value of over 200 GHz) is selected, based on a trade-off between speed and chip cost. Meanwhile it also has a benefit for providing an integrated microstrip model, which is utilized for the delay elements of the FFE. Chapter 3 illustrates the chip design of the high-speed backplane TX, consisting of a multiplexer (MUX) and a 5-tap FFE. The 4:1 MUX combines four lower rate streams into a high-speed differential NRZ signal up to 100 Gb/s as the FFE input. The 5-tap FFE is implemented with a novel topology for improved testability, such that the FFE performance can be individually characterized, in both frequency- and time-domain, which also helps to perform the coefficient optimization of the FFE. Different configurations for the gain cell in the FFE are compared. The gilbert configuration shows most advantages, in both a good high-frequency performance and an easy way to implement positive / negative amplification. The total chip, including the MUX and the FFE, consumes 750mW from a 2.5V supply and occupies an area of 4.4mm × 1.4 mm. In Chapter 4, the TX chip is demonstrated up to 84 Gb/s. First, the FFE performance is characterized in the frequency domain, showing that the FFE is able to work up to 84 Gb/s using duobinary formats. Second, the combination of the MUX and the FFE is tested. The equalized TX outputs are captured after different channels, for both NRZ and duobinary signaling at speeds from 64 Gb/s to 84 Gb/s. Then, by applying the duobinary RX 2, a serial electrical transmission link is demonstrated across a pair of 10 cm coax cables and across a 5 cm FX-2 differential stripline. The 5-tap FFE compensates a total loss between the TX and the RX chips of about 13.5 dB at the Nyquist frequency, while the RX receives the equalized signal and decodes the duobinary signal to 4 quarter rate NRZ streams. This shows a chip-to-chip data link with a bit error rate (BER) lower than 10−11. Last, the electrical data transmission between the TX and the RX over two commercial backplanes is demonstrated. An error-free, serial duobinary transmission across a commercial Megtron 6, 11.5 inch backplane is demonstrated at 48 Gb/s, which indicates that duobinary outperforms NRZ for attaining higher speed or longer reach backplane applications. Later on, using an ExaMAX® backplane demonstrator, duobinary transmission performance is verified and the maximum allowed channel loss at 40 Gb/s transmission is explored. The eye diagram and BER measurements over a backplane channel up to 26.25 inch are performed. The results show that at 40 Gb/s, a total channel loss up to 37 dB at the Nyquist frequency allows for error-free duobinary transmission, while a total channel loss of 42 dB was overcome with a BER below 10−8. An overview of the conclusions is summarized in Chapter 5, along with some suggestions for further research in this field. (1) The duobinary receiver was developed by my colleague Timothy De Keulenaer, as described in his PhD dissertation. (2) Described in the PhD dissertation of Timothy De Keulenaer

High Speed Reconfigurable NRZ/PAM4 Transceiver Design Techniques

While the majority of wireline standards use simple binary non-return-to-zero (NRZ) signaling, four-level pulse-amplitude modulation (PAM4) standards are emerging to increase bandwidth density. This dissertation proposes efficient implementations for high speed NRZ/PAM4 transceivers. The first prototype includes a dual-mode NRZ/PAM4 serial I/O transmitter which can support both modulations with minimum power and hardware overhead. A source-series-terminated (SST) transmitter achieves 1.2Vpp output swing and employs lookup table (LUT) control of a 31-segment output digital-to-analog converter (DAC) to implement 4/2-tap feed-forward equalization (FFE) in NRZ/PAM4 modes, respectively. Transmitter power is improved with low-overhead analog impedance control in the DAC cells and a quarter-rate serializer based on a tri-state inverter-based mux with dynamic pre-driver gates. The transmitter is designed to work with a receiver that implements an NRZ/PAM4 decision feedback equalizer (DFE) that employs 1 finite impulse response (FIR) and 2 infinite impulse response (IIR) taps for first post-cursor and long-tail ISI cancellation, respectively. Fabricated in GP 65-nm CMOS, the transmitter occupies 0.060mm² area and achieves 16Gb/s NRZ and 32Gb/s PAM4 operation at 10.4 and 4.9 mW/Gb/s while operating over channels with 27.6 and 13.5dB loss at Nyquist, respectively. The second prototype presents a 56Gb/s four-level pulse amplitude modulation (PAM4) quarter-rate wireline receiver which is implemented in a 65nm CMOS process. The frontend utilize a single stage continuous time linear equalizer (CTLE) to boost the main cursor and relax the pre-cursor cancelation requirement, requiring only a 2-tap pre-cursor feed-forward equalization (FFE) on the transmitter side. A 2-tap decision feedback equalizer (DFE) with one finite impulse response (FIR) tap and one infinite impulse response (IIR) tap is employed to cancel first post-cursor and longtail inter-symbol interference (ISI). The FIR tap direct feedback is implemented inside the CML slicers to relax the critical timing of DFE and maximize the achievable data-rate. In addition to the per-slice main 3 data samplers, an error sampler is utilized for background threshold control and an edge-based sampler performs both PLL-based CDR phase detection and generates information for background DFE tap adaptation. The receiver consumes 4.63mW/Gb/s and compensates for up to 20.8dB loss when operated with a 2- tap FFE transmitter. The experimental results and comparison with state-of-the-art shows superior power efficiency of the presented prototypes for similar data-rate and channel loss. The usage of proposed design techniques are not limited to these specific prototypes and can be applied for any wireline transceiver with different modulation, data-rate and CMOS technology

Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall

abstract: The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon. A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

차세대 자동차용 카메라 데이터 통신을 위한 비대칭 동시 양방향 송수신기의 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 정덕균.본 학위 논문에서는 차세대 자동차용 카메라 링크를 위해 높은 속도의 4레벨 펄스 진폭 변조 신호와 낮은 속도의 2레벨 펄스 진폭 변조 신호를 통신하는 비대칭 동시 양방향 송수신기의 설계 기술에 대해 제안하고 검증되었다. 첫번째 프로토타입 설계에서는, 10B6Q 직류 밸런스 코드를 탑재한 4레벨 펄스 진폭 변조 송신기와 고정된 데이터와 참조 레벨을 가지는 4레벨 펄스 진폭 변조 적응형 수신기에 대한 내용이 기술되었다. 4레벨 펄스 진폭 변조 송신기에서는 교류 연결 링크 시스템에 대응하기 위한 면적 및 전력 효율성이 좋은 10B6Q 코드가 제안되었다. 이 코드는 직류 밸런스를 맞추고 연속적으로 같은 심볼을 가지는 길이를 6개로 제한 시킨다. 비록 여기서는 입력 데이터 길이 10비트를 사용하였지만, 제안된 기술은 카메라의 다양한 데이터 타입에 대응할 수 있도록 입력 데이터 길이에 대한 확장성을 가진다. 반면, 4레벨 펄스 진폭 변조 적응형 수신기에서는, 샘플러의 옵셋을 최적으로 제거하여 더 낮은 비트에러율을 얻기 위해서, 기존의 데이터 및 참조 레벨을 조절하는 대신, 이 레벨들은 고정시키고 가변 게인 증폭기를 적응형으로 조절하도록 하였다. 상기 10B6Q 코드 및 고정 데이터 및 참조레벨 기술을 가진 프로토타입 칩들은 40 나노미터 상호보완형 메탈 산화 반도체 공정으로 제작되었고 칩 온 보드 형태로 평가되었다. 10B6Q 코드는 합성 게이트 숫자는 645개와 함께 단 0.0009 mm2 의 면적 만을 차지한다. 또한, 667 MHz 동작 주파수에서 단 0.23 mW 의 전력을 소모한다. 10B6Q 코드를 탑재한 송신기에서 8-Gb/s 4레벨 펄스 진폭 변조 신호를 고정 데이터 및 참조 레벨을 가지는 적응형 수신기로 12-m 케이블 (22-dB 채널 로스) 을 통해서 보낸 결과 최소 비트 에러율 108 을 달성하였고, 비트 에러율 105 에서는 아이 마진이 0.15 UI x 50 mV 보다 크게 측정되었다. 송수신기를 합친 전력 소모는 65.2 mW (PLL 제외) 이고, 성과의 대표수치는 0.37 pJ/b/dB 를 보여주었다. 첫번째 프로토타입 설계을 포함하여 개선된 두번째 프로토타입 설계에서는, 12-Gb/s 4레벨 펄스 진폭 변조 정방향 채널 신호와 125-Mb/s 2레벨 펄스 진폭 변조 역방향 채널 신호를 탑재한 비대칭 동시 양방향 송수신기에 대해 기술되고 검증되었다. 제안된 넓은 선형 범위를 가지는 하이브리드는 gmC 저대역 통과 필터와 에코 제거기와 함께 아웃바운드 신호를 24 dB 이상 효율적으로 감소시켰다. 또한, 넓은 선형 범위를 가지는 하이브리드와 함께 게인 감소기를 형성하게 되는 선형 범위 증폭기를 통해 4레벨 펄스 진폭 변조 신호의 선형성과 진폭의 트레이드 오프 관계를 깨는 것이 가능하였다. 동시 양방향 송수신기 칩은 40 나노미터 상호보완형 메탈 산화 반도체 공정으로 제작되었다. 상기 설계 기술들을 이용하여, 4레벨 펄스 진폭 변조 및 2레벨 펄스 진폭 변조 송수신기 모두 5m 채널 (채널 로스 15.9 dB) 에서 1E-12 보다 낮은 비트 에러율을 달성하였고, 총 78.4 mW 의 전력 소모를 기록하였다. 종합적인 송수신기는 성과 대표지표로 0.41 pJ/b/dB 와 함께 동시 양방향 통신 아래에서 4레벨 펄스 진폭 변조 신호 및 2레벨 펄스 진폭 변조 신호 각각에서 아이 마진 0.15 UI 와 0.57 UI 를 달성하였다. 이 수치는 성과 대표지표 0.5 이하를 가지는 기존 동시 양방향 송수신기와의 비교에서 최고의 아이 마진을 기록하였다.In this dissertation, design techniques of a highly asymmetric simultaneous bidirectional (SB) transceivers with high-speed PAM-4 and low-speed PAM-2 signals are proposed and demonstrated for the next-generation automotive camera link. In a first prototype design, a PAM-4 transmitter with 10B6Q DC balance code and a PAM-4 adaptive receiver with fixed data and threshold levels (dtLevs) are presented. In PAM-4 transmitter, an area- and power-efficient 10B6Q code for an AC coupled link system that guarantees DC balance and limited run length of six is proposed. Although the input data width of 10 bits is used here, the proposed scheme has an extensibility for the input data width to cover various data types of the camera. On the other hand, in the PAM-4 adaptive receiver, to optimally cancel the sampler offset for a lower BER, instead of adjusting dtLevs, the gain of a programmable gain amplifier is adjusted adaptively under fixed dtLevs. The prototype chips including above proposed 10B6Q code and fixed dtLevs are fabricated in 40-nm CMOS technology and tested in chip-on-board assembly. The 10B6Q code only occupies an active area of 0.0009 mm2 with a synthesized gate count of 645. It also consumes 0.23 mW at the operating clock frequency of 667 MHz. The transmitter with 10B6Q code delivers 8-Gb/s PAM-4 signal to the adaptive receiver using fixed dtLevs through a lossy 12-m cable (22-dB channel loss) with a BER of 1E-8, and the eye margin larger than 0.15 UI x 50 mV is measured for a BER of 1E-5. The proto-type chips consume 65.2 mW (excluding PLL), exhibiting an FoM of 0.37 pJ/b/dB. In a second prototype design advanced from the first prototypes, An asymmetric SB transceivers incorporating a 12-Gb/s PAM-4 forward channel and a 125-Mb/s PAM-2 back channel are presented and demonstrated. The proposed wide linear range (WLR) hybrid combined with a gmC low-pass filter and an echo canceller effectively suppresses the outbound signals by more than 24dB. In addition, linear range enhancer which forms a gain attenuator with WLR hybrid breaks the trade-off between the linearity and the amplitude of the PAM-4 signal. The SB transceiver chips are separately fabricated in 40-nm CMOS technology. Using above design techniques, both PAM-4 and PAM-2 SB transceivers achieve BER less than 1E-12 over a 5-m channel (15.9 dB channel loss), consuming 78.4 mW. The overall transceivers achieve an FoM of 0.41 pJ/b/dB and eye margin (at BER of 1E-12) of 0.15 UI and 0.57 UI for the forward PAM-4 and back PAM-2 signals, respectively, under SB communication. This is the best eye margin compared to the prior art SB transceivers with an FoM less than 0.5.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 DISSERTATION ORGANIZATION 4 CHAPTER 2 BACKGROUND ON AUTOMOTIVE CAMERA LINK 6 2.1 OVERVIEW 6 2.2 SYSTEM REQUIREMENTS 10 2.2.1 CHANNEL 10 2.2.2 POWER OVER DIFFERENTIAL LINE (PODL) 12 2.2.3 AC COUPLING AND DC BALANCE CODE 15 2.2.4 SIMULTANEOUS BIDIRECTIONAL COMMUNICATION 18 2.2.4.1 HYBRID 18 2.2.4.2 ECHO CANCELLER 20 2.2.5 ADAPTIVE RECEIVE EQUALIZATION 22 CHAPTER 3 AREA AND POWER EFFICIENT 10B6Q ENCODER FOR DC BALANCE 25 3.1 INTRODUCTION 25 3.2 PRIOR WORKS 28 3.3 PROPOSED AREA- AND POWER-EFFICIENT 10B6Q PAM-4 CODER 30 3.4 DESIGN OF THE 10B6Q CODE 33 3.4.1 PAM-4 DC BALANCE 35 3.4.2 PAM-4 TRANSITION DENSITY 35 3.4.3 10B6Q DECODER 37 3.5 IMPLEMENTATION AND MEASUREMENT RESULTS 40 CHAPTER 4 PAM-4 TRANSMITTER AND ADAPTIVE RECEIVER WITH FIXED DATA AND THRESHOLD LEVELS 45 4.1 INTRODUCTION 45 4.2 PRIOR WORKS 47 4.3 ARCHITECTURE AND IMPLEMENTATION 49 4.2.1 PAM-4 TRANSMITTER 49 4.2.2 PAM-4 ADAPTIVE RECEIVER 52 4.3 MEASUREMENT RESULTS 62 CHAPTER 5 ASYMMETRIC SIMULTANEOUS BIDIRECTIONAL TRANSCEIVERS USING WIDE LINEAR RANGE HYBRID 68 5.1 INTRODUCTION 68 5.2 PRIOR WORKS 70 5.3 WIDE LINEAR RANGE (WLR) HYBRID 75 5.3 IMPLEMENTATION 78 5.3.1 SERIALIZER (SER) DESIGN 78 5.3.2 DESERIALIZER (DES) DESIGN 79 5.4 HALF CIRCUIT ANALYSIS OF WLR HYBRID AND LRE 82 5.5 MEASUREMENT RESULTS 88 CHAPTER 6 CONCLUSION 97 BIBLIOGRAPHY 99 초 록 106박

A 2-40 Gb/s PAM4/NRZ dual-mode wireline transmitter with 4:1 MUX in 65-nm CMOS

This paper presents a 2-40 Gb/s dual-mode wireline transmitter supporting the four-level pulse amplitude modulation (PAM4) and non-return-to-zero (NRZ) modulation with a multiplexer (MUX)-based two-tap feed-forward equalizer (FFE). An edge-acceleration technique is proposed for the 4:1 MUX to increase the bandwidth. By utilizing a dedicated cascode current source, the output swing can achieve 900 mV with a level deviation of only 0.12% for PAM4. Fabricated in a 65-nm CMOS process, the transmitter consumes 117 mW and 89 mW at 40 Gb/s in PAM4 and NRZ at 1.2 V supply. © 2018, Institute of Electronics Engineers of Korea. All rights reserved

Advanced Signal Processing for Pulse-Amplitude Modulation Optical Transmission Systems

[ES] Los sistemas de transmisión óptica no-coherente se emplean actualmente en las redes ópticas de corto alcance (< 80 km), como son las redes de ámbito metropolitano. La implementación más común en el estado del arte se basa en sistemas que emplean multiplexación por división en longitud de onda (WDM, wavelength division multiplexing) de cuatro longitudes de onda (¿) proporcionando un régimen binario de 100 Gbps (4¿×25 Gbps). En los últimos años, los sistemas de transmisión ópticos no-coherentes están evolucionando desde 100 Gbps a 400 Gbps (4¿×100 Gbps). Dado que este mercado comprende un gran número de sistemas, el coste es un parámetro importante que debe ser lo más bajo posible. El objetivo de esta tesis es investigar distintos aspectos del procesado de señal en general y, específicamente, investigar nuevas técnicas de procesado digital de señal (DSP, digital signal processing) que puedan ser utilizadas en sistemas de transmisión óptica no-coherentes empleando la modulación por amplitud de pulsos (PAM, pulse-amplitude modulation). Para que una técnica DSP sea interesante en el contexto de una red óptica WDM no-coherente, esta debe mitigar de manera efectiva al menos una de las tres limitaciones principales que afectan a estos sistemas: limitaciones de ancho de banda, limitaciones por dispersión cromática (CD), y el ruido. En esta tesis se proponen y examinan una serie de algoritmos cuyo su rendimiento es analizado mediante simulación y experimentalmente en laboratorio: - Feed-forward equalizer (FFE): este es el esquema de ecualización más común que se emplea principalmente en las transmisiones ópticas no-coherentes de alto régimen binario. Puede compensar grandes limitaciones en el ancho de banda. - Estimación de la secuencia de máxima verosimilitud (MLSE): el MLSE es un detector óptimo y, por lo tanto, proporciona las mejores prestaciones en detección cuando se abordan las limitaciones por CD y de ancho de banda. - Conformación geométrica de la constelación: en los esquemas de modulación de intensidad óptica multinivel, la distancia entre los niveles de amplitud puede ajustarse adecuadamente (de manera que no son equidistantes) a fin de aumentar la tolerancia de la señal frente al ruido. - Conformación probabilística: técnica diseñada específicamente para esquemas de modulación multinivel. Esta técnica ajusta la probabilidad de cada nivel de amplitud de modo que se incrementa la tolerancia al ruido óptico. - Señalización de respuesta parcial (PRS, partial signaling response): este es un enfoque basado en DSP donde una interferencia entre símbolos (ISI, inter-symbol interference) controlada es introducida intencionalmente de tal manera que la señal resultante requiere menos ancho de banda. La técnica PRS puede adaptarse para combatir también el efecto de CD. - Pre-énfasis digital (DPE, digital pre-emphasis): esta técnica consiste en aplicar el inverso de la función de transferencia del sistema a la señal en el transmisor, lo que reduce el impacto de las limitaciones de ancho de banda en el receptor. - Modulación con codificación Trellis (TCM, Trellis-coded modulation): esquema de modulación que combina elementos de corrección de errores (FEC, forward error correction) con técnicas de partición en conjuntos y modulación multidimensional para generar una señal más resistente al ruido. - Modulación multidimensional por partición en conjuntos: muy similar a TCM, pero sin ningún elemento FEC. Tiene menos ganancias que TCM en términos de tolerancia al ruido, pero no es tan sensible al ISI. Utilizando estas técnicas, esta tesis demuestra que es posible lograr una transmisión óptica con régimen binario de 100 Gbps/¿ empleando componentes de bajo coste. En esta tesis también demuestra regímenes binarios de más de 200 Gbps, lo que indica que la transmisión óptica no-coherente con modulación PAM puede ser una solución viable y eficiente en coste[CA] Actualment, s'utilitzen sistemes òptics no coherents en xarxes òptiques de curt abast ( < 80 km), com són les xarxes d'àmbit metropolità. La implementació més comuna que podem trobar en l'estat de l'art es correspon amb sistemes emplenant multiplexació per divisió en longitud d'ona (WDM, wavelength division multiplexing) de quatre longituds d'ona (¿) proporcionant un règim binari de 100 Gbps (4¿×25 Gbps). En els últims anys, els sistemes de transmissió òptica no-coherents han evolucionat des de 100 Gbps cap a 400 Gbps (100 Gbps/¿). Atès que el mercat de sistemes de curt abast compren un gran volum de dispositius òptics instal·lats, el cost unitari és molt important i ha de ser el més baix possible. L'objectiu d'aquesta tesi és analitzar aspectes del processament de senyal en general i, específicament, investigar noves tècniques de processament digital de senyal (DSP, digital signal processing) que puguen ser utilitzades en sistemes de transmissió òptica no-coherent que utilitzen la modulació per amplitud d'impulsos (PAM, pulse-amplitude modulation). Per tal que una tècnica DSP es considere interessant per a una xarxa òptica WDM no-coherent, aquesta ha de mitigar efectivament almenys una de les tres principals limitacions que afecten aquests sistemes: limitacions d'ample de banda, limitacions per dispersió cromàtica (CD), i el soroll. En aquesta tesi s'examinen una sèrie d'algoritmes, el seu rendiment s'analitza per simulació i experimentalment en laboratori: - Feed-forward equalizer (FFE): aquest és l'esquema d'equalització més comú i s'utilitza bàsicament en les transmissions òptiques no coherents d'alt règim binari. Pot compensar grans quantitats de limitacions d'ample de banda. - Estimació de la seqüència de probabilitat màxima (MLSE): el MLSE és un detector òptim i, per tant, proporciona el millor rendiment quan es tracta de limitacions d'ample de banda i de CD. - Conformació geomètrica de la constel·lació: en esquemes de modulació òptica d'intensitat multinivell es pot ajustar la distància entre els nivells d'amplitud (de manera que ja no són equidistants) per augmentar la tolerància del senyal al soroll. - Conformació probabilística: una tècnica dissenyada específicament per als esquemes de modulació multinivell; ajusta la probabilitat de cada nivell d'amplitud de manera que augmenta la tolerància al soroll òptic. - Senyalització de resposta parcial (PRS, partial signaling response): és un enfocament basat en DSP on la interferència entre símbols (ISI, inter-symbol interference) controlada s'introdueix intencionalment de manera que el senyal resultant requereix menys ample de banda. La tècnica PRS es pot adaptar per combatre els efectes del CD. - Pre-èmfasi digital (DPE, digital pre-emphasis): aquesta tècnica consisteix a aplicar la inversió de la funció de transferència del sistema a la senyal en el transmissor de manera que es redueix l'impacte de les limitacions d'ample de banda en la senyal en el receptor. - Modulació amb codificació Trellis (TCM, Trellis-coded modulation): esquema de modulació que combina els elements de correcció d'errors avançats (FEC, forward error correction) amb tècniques de partionament de conjunts i modulació multidimensional per generar un senyal més resistent al soroll. - Modulació multidimensional per partició en conjuntes: molt similar a TCM però sense elements FEC. Té guanys menors que TCM en termes de tolerància al soroll, però no és tan sensible a l'ISI. Mitjançant l'ús d'aquestes tècniques, aquesta tesi demostra que és possible aconseguir una transmissió òptica amb un règim binari de 100 Gbps/¿ utilitzant components de baix cost. Esta tesi també demostra règims binaris de més de 200 Gbps, el que indica que la tecnologia no-coherent amb modulació PAM és una solució viable i eficient en cost per a una nova generació de sistemes transceptors òptics WDM funcionant a 800 Gbps (4¿×200 G[EN] Non-coherent optical transmission systems are currently employed in short-reach optical networks (reach shorter than 80 km), like metro networks. The most common implementation in the state-of-the-art is the four wavelength (¿) 100 Gbps (4¿×25 Gbps) wavelength division multiplexing (WDM) transceiver. In recent years non-coherent optical transmissions are evolving from 100 Gbps to 400 Gbps (4¿×100 Gbps). Since in the short-reach market the volume of optical devices being deployed is very large, the cost-per-unit of the devices is very important, and it should be as low as possible. The goal of this thesis is to investigate some general signal processing aspects and, specifically, digital signal processing (DSP) techniques required in non-coherent pulse-amplitude modulation (PAM) optical transmission, and also to investigate novel algorithms which could be applied to this application scenario. In order for a DSP technique to be considered an interesting solution for non-coherent WDM optical networks it has to effectively mitigate at least one of the three main impairments affecting such systems: bandwidth limitations, chromatic dispersion (CD) and noise (in optical or electrical domain). A series of algorithms are proposed and examined in this thesis, and their performance is analyzed by simulation and also experimentally in the laboratory: - Feed-forward equalization (FFE): this is the most common equalizer and it is basically employed in every high-speed non-coherent optical transmission. It can compensate high bandwidth limitations. - Maximum likelihood sequence estimation (MLSE): the MLSE is the optimum detector and thus provides the best performance when it comes to dealing with CD and bandwidth limitations. - Geometrical constellation shaping: in multilevel optical intensity modulation schemes the distance between amplitude levels can be adjusted (such that they are no longer equidistant) in order to increase the signal's tolerance to noise. - Probabilistic shaping: another technique designed specifically for multilevel modulation schemes; it adjusts the probability of each amplitude level such that the tolerance to optical noise is increased. - Partial response signaling (PRS): this is a DSP-based approach where a controlled inter-symbol interference (ISI) is intentionally introduced in such a way that the resulting signal requires less bandwidth. PRS can be customized to also mitigate CD impairment, effectively increasing transmission distances up to three times. - Digital pre-emphasis (DPE): this technique consists in applying the inverse of the transfer function of the system to the signal at the transmitter side which reduces the impact of bandwidth limitations on the signal at the receiver side. - Trellis-coded modulation (TCM): a modulation scheme that combines forward error correction (FEC) elements with set-partitioning techniques and multidimensional modulation to generate a signal that is more resistant to noise. - Multidimensional set-partitioned modulation: very similar with TCM but without any FEC elements. It has lower gains than TCM in terms of noise tolerance but is not so sensitive to ISI. By using the techniques enumerated above, this thesis demonstrates that is possible to achieve 100 Gbps/¿ optical transmission bitrate employing cost-effective components. Even more, bitrates higher than 200 Gbps are also demonstrated, indicating that non-coherent PAM is a viable cost-effective solution for next-generation 800 Gbps (4¿×200 Gbps) WDM transceivers.Prodaniuc, C. (2019). Advanced Signal Processing for Pulse-Amplitude Modulation Optical Transmission Systems [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/117315TESI