High-speed high-resolution low-power self-calibrated digital-to-analog converters

High-speed and high-resolution low-power digital-to-analog converters (DACs) are basic design blocks in many applications. Several obvious conflicting requirements such as high-speed, high-resolution, low-power, and small-area have to be satisfied. In this dissertation, a modular architecture for continuous self-calibrating DACs is proposed to satisfy the above requirements. This includes a redundant-cell-relay continuous self-calibration scheme. Several prototype DACs were implemented with self-calibration schemes. Also a DAC synthesis algorithm using a direct-mapping method and the modular structure was developed and implemented in the Cadence SKILL programming language.;One of the prototypes is a 250MS/s 8-bit continuous self-calibrated DAC that has been implemented in TSMC\u27s 0.25mu single poly five metal logic CMOS process. The structure of the self-calibrated current cell has high impedance and low sensitivity to output node voltage fluctuations. The chip has achieved +0.15/-0.1 LSB DNL, -0.6/+0.4 LSB INL, and 55dB SFDR with a lower input frequency at a conversion rate of 250MS/s. It consumes 8 mW of power in a 0.13 mm2 die area.;Glitches caused by switching of the calibration clock degrade the SFDR especially in high-speed applications. A new redundant-cell-relay continuous self-calibration scheme was proposed to reduce the glitches. Simulation results showed that the glitch energy is reduced 10 fold over existing schemes. A 10-bit DAC was implemented in the 0.25mu CMOS process mentioned above. +/-0.5 LSB INL and -0.45/+0.2 LSB DNL were measured and 70dB SFDR was achieved with a lower input frequency at a 250MS/s conversion rate. Up to the Nyquist rate, the SFDR is above 53dB at a conversion rate of 200MS/s. The DAC dissipates 8mW in a 0.3mm2 die area. The testing results verified the redundant-cell-relay continuous self-calibration for high-speed high-resolution low-power and low-cost DACs.;Additionally, a DAC synthesis algorithm was developed based on a direct mapping method. Given the specifications such as the DAC\u27s resolution, full range scale and technology, the synthesizer will map them directly into pre-existing functional blocks implemented in the DAC synthesis libraries. The program will then synthesize the schematic and layout that closely meet the given specifications

Dynamic calibration of current-steering DAC

The demand for high-speed communication systems has dramatically increased during the last decades. Working as an interface between the digital and analog world, Digital-to-Analog converters (DACs) are becoming more and more important because they are a key part which limits the accuracy and speed of an overall system. Consequently, the requirements for high-speed and high-accuracy DACs are increasingly demanding. It is well recognized that dynamic performance of the DACs degrades dramatically with increasing input signal frequencies and update rates. The dynamic performance is often characterized by the spurious free dynamic range (SFDR). The SFDR is determined by the spectral harmonics, which are attributable to system nonlinearities.;A new calibration approach is presented in this thesis that compensates for the dynamic errors in performance. In this approach, the nonlinear components of the input dependent and previous input code dependent errors are characterized, and correction codes that can be used to calibrate the DAC for these nonlinearities are stored in a two-dimensional error look-up table. A series of pulses is generated at run time by addressing the error look-up table with the most significant bits of the Boolean input and by using the corresponding output to drive a calibration DAC whose output is summed with the original DAC output. The approach is applied at both the behavioral level and the circuit level in current-steering DAC.;The validity of this approach is verified by simulation. These simulations show that the dynamic nonlinearities can be dramatically reduced with this calibration scheme. The simulation results also show that this calibration approach is robust to errors in both the width and height of calibration pulses.;Experimental measurement results are also provided for a special case of this dynamic calibration algorithm that show that the dynamic performance can be improved through dynamic calibration, provided the mean error values in the table are close to their real values

Design techniques for high-performance current-steering digital-to-analog converters

Digital-to-Analog Converter (DAC) is a crucial building block limiting the accuracy and speed of many signal processing and telecommunication systems. To achieve high speed and high resolution, the current-steering architecture is almost exclusively used. Three important issues for current-steering DAC design are addressed in this dissertation. In a current-steering DAC design, it is essential that a designer determine the minimum required current source accuracy to overcome random current mismatch and achieve high linearity with guaranteed yield. Simple formulas are derived that clearly exhibit the relationship between the standard deviation of unit current sources, the bits of resolution, the INL/DNL, and the soft yield of DAC arrays. It is shown that these formulas are very effective for optimizing the DAC segmentation so as to achieve high performance and high yield with minimal area and power consumption. To overcome random mismatch effects without any trimming, the current source array of a high-accuracy DAC is usually rather large, causing the gradient errors in these arrays to become significant. How gradient errors affect the DAC linearity and how to compensate for them through switching sequence optimization is analyzed in the second part of this dissertation. To overcome technology barriers, relax the requirements on layout and reduce the sensitivities of DACs to process, temperature and aging, calibration is emerging as an attractive solution for the next-generation high-performance DACs, especially as process feature size keeps shrinking and supply voltage is reduced correspondingly. A new foreground calibration technique suitable for low-voltage environment is presented in the third part of this dissertation. It can effectively compensate for current source mismatches, and achieve high linearity with small die size and low power consumption. The dynamic performance of the DAC is also improved due to the dramatic reduction of parasitic effects. To demonstrate this technique, a 14-bit prototype was designed and fabricated in a 0.13u digital CMOS process. It is the first 14-bit CMOS DAC ever reported that operates with a single 1.5V power supply, occupies an active area less than 0.1mm2, and requires only 16.7mW at 100MHz sampling rate, but still maintains state-of-art linearity and speed

An ultra wide temperature range R-2R based 8 bit D/A converter for 90nm CMOS technology

Digital-to-analog converters have a wide range of applications from converting stored digital/audio signals to data processing and to data acquisition systems. Another application area could be a supporting building block in either cooled or un-cooled Read-out integrated circuits (ROICs). For this aspect, the capability of ultra wide temperature range operation may prove useful providing freedom to the designer and the consumer. In this thesis, design of an 8-bit, fully binary R-2R based digital-to-analog converter is realized with 90nm CMOS technology to operate in a wide temperature range (-200°C to 120°C) to be used in an ongoing Digital Read-out Integrated Circuit (DROIC) for infrared (IR) imaging systems. UWT range of operation is obtained via a temperature compensated voltage reference generator circuit consisting of only MOSFETs. In order to aid the matching of the resistors, a common-centroid layout technique is applied to the resistor core of the circuit which eliminates the process gradients. TSMC's 90nm 1 poly, 9 metal Mixed – Signal RF technology and a power supply of 1.2V are used for this design. For accuracy, the best performance is obtained at the room temperature where the fastest operation is possible at cryogenic temperatures at the expense of precision. It has a DNL and INL of ±0.3LSB at room temperature and ±0.45LSB at 120°C. The DAC can operate up to 20MHz. The circuit dissipates only 0.43mW in full scale range at cryogenic temperatures where 1.1mW at room. It occupies a chip area of only 0.015mm2 [square millimetre]

Analysis and Design of High-Speed A/D Converters in SiGe Technology

Mixed-signal systems play a key role in modern communications and electronics. The quality of A/D and D/A conversions deeply affects what we see and what we hear in the real world video and radio. This dissertation deals with high-speed ADCs: a 5-bit 500-MSPS ADC and an 8-bit 2-GSPS ADC. These units can be applied in flat panel display, image enhancement and in high-speed data link. To achieve the state-of-the-art performance, we employed a 0.13-μm/2.5-V 210-GHz (unity-gain frequency) BiCMOS SiGe process for all the implementations. The circuit building blocks, such as the Track-and-Hold circuit (T/H) and the comparator, required by an ADC not only benefit from SiGe's superior ultra-high frequency properties but also by its power drive capability. The T/H described here achieved a dynamic performance of 8-bit accuracy at 2-GHz Nyquist rate with an input full scale range of 1 Vp-p. The T/H consumed 13 mW of power. The unique 4-in/2-out comparator was made of fully differential emitter couple pairs in order to operate at such a high frequency. Cascaded cross-coupled amplifier core was employed to reduce Miller effect and to avoid collector-emitter breakdown of the HBTs. We utilized the comparator interpolation technique between the preamplifer stages and the latches to reduce the total power dissipated by the comparator array. In addition, we developed an innovative D/A conversion and analog subtraction approach necessary for two-step conversion by using a bipolar pre-distortion technique. This innovation enabled us to decrease the design complexity in the subranging process of a two-step ADC. The 5-bit interpolating ADC operated at 2-GSPS achieved a differential nonlinearity (DNL) of 0.114 LSB and an integral nonlinearity (INL) of 0.076 LSB. The effective number of bits (ENOBs) are 4.3 bits at low frequency and 4.1 bits near Nyquist rate. The power dissipation was reduced more than half to 66.14 mW, with comparator interpolation. The 8-bit two-step interpolating ADC operated at 500-MSPS. It achieved a DNL of 0.33 LSB and an INL of 0.40 LSB with a power consumption of 172 mW. The ENOBs are 7.5 bits at low frequency and 6.9 bits near Nyquist rate

"Design and verification of a digitally controlled output stage for automotive safety applications"

In these last decades the importance of electronics in automotive environment had an exponential increase. Electronic Integrated Circuits (ICs) are now playing a primary role in the economy of vehicles, especially since special laws and strict safety requirements have been introduced. The aim of the thesis, developed within Austramicrosystem design centre of Navacchio (PI), is the design and the verification of a digitally controlled output stage. Output stages are the final components of many sensor-based ICS. In fact their typical typical signal-chain starts from the sensing of a physical phenomenon, passing by its transduction in an electrical quantity, its digital conversion and processing, and ends with the drive of an actuator. The task of an output stage is to interpret the input digital signal and consequently drive an actuator. The target of this work was to improve the performances of the current output stage company solutions. This target has been achieved through the development and realization of a digitally-controlled loop. The proposed solution guarantees a performance improvement and adds the possibility to cyclically monitor the output voltage, detecting issues and reporting errors. A control algorithm has been developed and validated through its insertion in a mathematical modeling of the system. Then, to experimentally validate this control algorithm, an Integrated Circuit has been designed, realized and lastly measured. This thesis follows the workflow behind the realization of the Integrated Circuit and its successive measurement

New device matching strategies for high-precision analog and mixed-signal circuits

For several decades, technology scaling has brought many orders of magnitude improvements in digital CMOS performance and similar economic benefits to consumers. Feature size is quickly approaching nanometer scale, and the associated large variability imposes grand challenges in achieving reliable and robust operation. This is especially so for high-precision analog and mixed-signal circuits since they have always relied on accurate device matching which will not be available in nanometer CMOS or emerging technologies. This dissertation is aiming to develop design methodologies for overcoming such grand challenges without the conventional matching requirements. The underlining hypothesis is that, from a population of devices with significant variability, correct interconnection and sequencing can produce an effective system level matching that is several orders of magnitude better than the original devices. The optimal solution is non-deterministic polynomial-time hard but a simple ordered element matching strategy based on ordered statistics produces dramatically improved matching. Practical implementation of the new matching strategy is demonstrated on a 15-bit binary-weighted current-steering digital-to-analog converter design in a 130nm CMOS technology. The core area of the chip is less than 0.42mm2, among which the MSB current source area is well within 0.021mm2. Measurement results have shown that the differential nonlinearity and integral nonlinearity can be reduced from 9.85LSB and 17.41LSB to 0.34LSB and 0.77LSB, respectively

Mixed-signal integrated circuits design and validation for automotive electronics applications

Automotive electronics is a fast growing market. In a field primarily dominated by mechanical or hydraulic systems, over the past few decades there has been exponential growth in the number of electronic components incorporated into automobiles. Partly thanks to the advance in high voltage smart power processes in nowadays cars is possible to integrate both power/high voltage electronics and analog/digital signal processing circuitry thus allowing to replace a lot of mechanical systems with electro-mechanical or fully electronic ones. High level modeling of complex electronic systems is gaining importance relatively to design space exploration, enabling shorter design and verification cycles, allowing reduced time-to-market. A high level model of a resistor string DAC to evaluate nonlinearities has been developed in MATLAB environment. As a test case for the model, a 10 bit resistive DAC in 0.18um is designed and the results were compared with the traditional transistor level approach. Then we face the analysis and design of a fundamental block: the bandgap voltage reference. Automotive requirements are tough, so the design of the voltage reference includes a pre-regulation part of the battery voltage that allows to enhance overall performances. Moreover an analog integrated driver for an automotive application whose architecture exploits today’s trends of analog-digital integration allowing a greater range of flexibility allowing high configurability and fast prototipization is presented. We covered also the mixed-signal verification approach. In fact, as complexity increases and mixed-signal systems become more and more pervasive, test and verification often tend to be the bottleneck in terms of time effort. A complete flow for mixed-signal verification using VHDL-AMS modeling and Python scripting is presented as an alternative to complex transistor level simulations. Finally conclusions are drawn

Power and spectrally efficient integrated high-speed LED drivers for visible light communication

Recent trends in mobile broadband indicates that the available radio frequency (RF) spectrum will not be enough to support the data requirements of the immediate future. Visible light communication, which uses visible spectrum to transmit wirelessly could be a potential solution to the RF ’Spectrum Crunch’. Thus there is growing interest all over the world in this domain with support from both academia and industry. Visible light communication( VLC) systems make use of light emitting diodes (LEDs), which are semiconductor light sources to transmit information. A number of demonstrators at different data capacity and link distances has been reported in this area. One of the key problems holding this technology from taking off is the unavailability of power efficient, miniature LED drive schemes. Reported demonstrators, mostly using either off the shelf components or arbitrary waveform generators (AWGs) to drive the LEDs have only started to address this problem by adopting integrated drivers designed for driving lighting installations for communications. The voltage regulator based drive schemes provide high power efficiency (> 90 %) but it is difficult to realise the fast switching required to achieve the Mbps or Gbps data rates needed for modern wireless communication devices. In this work, we are exploiting CMOS technology to realise an integrated LED driver for VLC. Instead of using conventional drive schemes (digital to analogue converter (DAC) + power amplifier or voltage regulators), we realised a current steering DAC based LED driver operating at high currents and sampling rates whilst maintaining power efficiency. Compared to a commercial AWG or discrete LED driver, circuit realised utilisng complementary metal oxide semiconductor (CMOS) technology has resulted in area reduction (29mm2). We realised for the first time a multi-channel CMOS LED driver capable of operating up to a 500 MHz sample rate at an output current of 255 mA per channel and >70% power efficiency. We were able to demonstrate the flexibility of the driver by employing it to realise VLC links using micro LEDs and commercial LEDs. Data rates up to 1 Gbps were achieved using this system employing a multiple input, multiple output (MIMO) scheme. We also demonstrated the wavelength division multiplexing ability of the driver using a red/green/blue commercial LED. The first integrated digital to light converter (DLC), where depending on the input code, a proportional number of LEDs are turned ON, realising a data converter in the optical domain, is also an output from this research. In addition, we propose a differential optical drive scheme where two output branches of a current DAC are used to drive two LEDs achieving higher link performance and power efficiency compared to single LED drive

Implémentation, ajustement laser et modélisation des convertisseurs numériques à analogique R2R

La conversion numérique à analogique -- Principales caractéristiques des CNA -- Algorithmes et architectures de conversion -- Techniques de linéarisation -- Le CNA R2R inversé -- Un CNA 14 bits ajusté au laser et fabriqué dans une technologie CMOS standard -- Puce -- Montage de test -- Notes et résultats de tests -- Une compensation améliorée pour les interrupteurs des CNA R2R inversés -- Modélisation des CNA R2R