Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters

Nowadays, the multi-standard wireless receivers and multi-format video processors have created a great demand for integrating multiple standards into a single chip. The multiple standards usually require several Analog to Digital Converters (ADCs) with different specifications. A promising solution is adopting a power and area efficient reconfigurable ADC with tunable bandwidth and dynamic range. The advantage of the reconfigurable ADC over customized ADCs is that its power consumption can be scaled at different specifications, enabling optimized power consumption over a wide range of sampling rates and resulting in a more power efficient design. Moreover, the reconfigurable ADC provides IP reuse, which reduces design efforts, development costs and time to market. On the other hand, software radio transceiver has been introduced to minimize RF blocks and support multiple standards in the same chip. The basic idea is to perform the analog to digital (A/D) and digital to analog (D/A) conversion as close to the antenna as possible. Then the backend digital signal processor (DSP) can be programmed to deal with the digital data. The continuous time (CT) bandpass (BP) sigma-delta ADC with good SNR and low power consumption is a good choice for the software radio transceiver. In this work, a proposed 10-bit reconfigurable ADC is presented and the non-overlapping clock generator and state machine are implemented in UMC 90nm CMOS technology. The state machine generates control signals for each MDAC stage so that the speed can be reconfigured, while the power consumption can be scaled. The measurement results show that the reconfigurable ADC achieved 0.6-200 MSPS speed with 1.9-27 mW power consumption. The ENOB is about 8 bit over the whole speed range. In the second part, a 2-bit quantizer with tunable delay circuit and 2-bit DACs are implemented in TSMC 0.13um CMOS technology for the 4th order CT BP sigma-delta ADC. The 2-bit quantizer and 2-bit DACs have 6dB SNR improvement and better stability over the single bit quantizer and DACs. The penalty is that the linearity of the feedback DACs should be considered carefully so that the nonlinearity doesn't deteriorate the ADC performance. The tunable delay circuit in the quantizer is designed to adjust the excess loop delay up to +/- 10% to achieve stability and optimal performance

Design techniques for high performance CMOS flash analog -to -digital converters.

This thesis describes research on very-high-sampling-rate, moderate-resolution, CMOS, analog-to-digital converters (ADCs). The sampling rate of an ADC can be extended through the use of a faster process technology (e.g., GaAs), or through time-interleaving. However, circuit techniques that extend the sampling rates of an ADC for a given CMOS technology, are still fundamentally required. Flash ADCs generally achieve the highest sampling rate. Architectures and building blocks of flash ADCs are investigated. The comparator is one of the most critical components in a flash ADC. New circuit techniques that improve comparator performance are proposed. The addition of on-chip, compact, low Q inductors improves the sampling speed of the comparators without an increase in power consumption. Compact inductors consume 1% of the die area required for conventional on-chip inductors. The value of inductance is optimized through the consideration of both tracking and regenerative time constants. A clocked-cascode structure in the preamplifier reduces kickback to the reference. The use of a reduced swing sampling clock further extends sampling rate. The use of minimum length transistors also helps to extend sampling speed and improve power efficiency. Offset correction is required even for moderate resolutions, because of the significant mismatch of minimum length transistors in deep-submicron CMOS. Comparator redundancy, DAC trimming at the comparator output, and DAC trimming at the reference input are proposed to calibrate comparator offset. Offset correction and calibration are optimized to maximize ADC yield and to minimize DNL and INL errors. Two non-interleaved prototype flash ADCs were designed, fabricated and tested. A 4 bit ADC was implemented in 0.18 mum TSMC CMOS and a 5 bit ADC was implemented in 90 nm Intel CMOS. The 4 bit ADC achieves a sampling rate of up to 4 GHz with a measured effective resolution of 3.89 bits. The ADC consumes 551 mW at 3 GS/s with a 1.5 GHz full power input, and of this, the analog portion consumes 78 mW. The 5 bit ADC also achieves a sampling rate of up to 4 GHz and an effective resolution of 4.28 effective bits. This ADC consumes 227 mW at 3.5 GS/s with 1 GHz full power input. The analog circuitry of the 5 bit ADC consumes 115 mW. Both these ADCs achieve over twice the sampling rate of recently published state-of-the-art, non-interleaved, low-resolution CMQS ADCs. (Abstract shortened by UMI.)Ph.D.Applied SciencesElectrical engineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/126254/2/3238051.pd