Design space exploration for minimizing multi-project wafer production cost,” ASPDAC

Abstract- Chip floorplan in a reticle for Multi-Project Wafer (MPW) plays a key role in deciding chip fabrication cost. In this paper 1, we propose a methodology to explore reticle flooplan design space to minimize MPW production cost, facilitated by a new cost model and an efficient reticle floorplanning method. It is shown that a good floorplan saves 47 % and 42 % production cost with respect to a poor floorplan for small and medium volume production, respectively. I