High Tolerance of Charge Pump Leakage Current in Integer-N PLL Frequency Synthesizer for 5G Networks

One of the most promising solutions for the future fifth generation communication systems is to utilize millimeter wave (mm-W) radio frequencies. There is, however, little works about Phase Locked Loop (PLL) frequency synthesizer designed for mm-W band frequency for 5G applications. This article discusses integer PLL architecture for frequency synthesis; it targets the highest range of 5G mmW [81-86] GHz using ultra-wide channel spacing of 1GHz. This work investigates the design of a third passive loop filter for frequency synthesizer using a Phase Frequency Detector and a current switch Charge Pump such as analog devices ADF4155. The critical performance for the Charge Pump depends on the leakage current produced by the technology of its transistors. This undesirable current can have a high impact on the loop stability. However, by optimizing PLL filter parameters, the synthesizer was able to tolerate up to 117 nA. With such a high leakage current, a high performance of the system was achieved. As a result, less than −71 dBc reference spur level at 50 MHz offset frequency was ensured and 3.23 µs settling time for a hopping frequency of 5 GHz was achieved

Design of low-power wideband frequency quadruplers based on transformer-coupled resonators for E-Band backhaul applications

This paper presents a mm-wave two-stage push-push BiCMOS frequency quadrupler for E-band wireless backhaul applications. To enhance gain-bandwidth product and overcome the limitations of classic push-push pairs, coupled resonators realized through low-k transformers are employed. A novel transformer layout is proposed for single-ended to differential conversion to achieve superior suppression of differential mismatches and enhanced gain. The measured prototype, fabricated in 55 nm BiCMOS technology, achieves a remarkable 27% fractional bandwidth around the center frequency of 74 GHz with a power consumption of 7 mW onl