Design of an optimized low-latency interrupt controller for IMS-DPU

Interrupt handling mechanism is an important function for multi-core system to work collaboratively. In this paper, an optimized low-latency interrupt controller is proposed to support a multi-core system IMS-DPU for high performance medical electronics equipment. Utilizing two interrupt models, the interrupt controller implements three different kinds of interrupts, shared peripheral interrupt (SPI), private peripheral interrupt (PPI) and software generated interrupt (SGI). The main feature of the controller is to distribute multiple interrupts across the cores of a multi-core system. In addition, our architecture supports several advanced features like interrupt pending and active state, interrupt preemption and nesting, interrupt grouping and security extension. The design in this study puts forward special optimization for performance enhancement in hardware structures, with the aim to support the combination of software stack and hardware stack, tail chaining and later arrivals. FPGA prototyping results justify the design. It is finally implemented with CSMC 180nm technology with 6.01K logic gates at working frequency of 200MHz.http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000341774100020&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701EICPCI-S(ISTP)