Current Sensing Completion Detection in Single-Rail Asynchronous Systems

In this article, an alternative approach to detecting the computation completion of combinatorial blocks in asynchronous digital systems is presented. The proposed methodology is based on well-known phenomenon that occurs in digital systems fabricated in CMOS technology. Such logic circuits exhibit significantly higher current consumption during the signal transitions than in the idle state. Duration of these current peaks correlates very well with the actual computation time of the combinatorial block. Hence, this fact can be exploited for separation of the computation activity from static state. The paper presents fundamental background of addressed alternative completion detection and its implementation in single-rail encoded asynchronous systems, the proposed current sensing circuitry, achieved simulation results as well as the comparison to the state-of-the-art methods of completion detection. The presented method promises the enhancement of the performance of an asynchronous circuit, and under certain circumstances it also reduces the silicon area requirements of the completion detection block

동기 회로에서 시간 오류를 고려한 공급전압 제어

학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 2. 최기영.Modern embedded systems are becoming more and more constrained by power consumption. While we require those systems to compute even more data at faster speed, lowering energy consumption is essential to preserve battery life as well as integrity of devices. Amongst many techniques to reduce power consumption of chips such as power gating, clock gating, etc., lowering the supply voltage (maybe reducing chips frequency) is known to be the most effective one. However, lowering the supply voltage of chips too much down to near the threshold voltage of transistors causes the logic delay to vary exponentially with intrinsic and extrinsic variations (process variations, temperature, aging, etc.) and thus forces the designer to set increased timing margin. This thesis proposes a technique for automatically adjusting the supply voltage to match the speed of a logic block with a given time constraint. Depending on process and temperature variations, our technique chooses the minimum supply voltage to satisfy the timing constraint defined by the designer. This allows him/her to reduce the default supply voltage of the logic block and thus save power. In our experiments at the 28/32nm technology node, we succeeded in reducing the logic block power by 52% on average by varying the supply voltage between 0.55V and 1V, while the nominal supply voltage is 1.05V.Abstract Contents List of Figures List of Tables Chapter 1 Introduction 1 Chapter 2 Background 5 1.1 Near-Threshold Computing 5 1.2 Current Sensing Completion Detection 7 Chapter 3 Proposed Approach 12 Chapter 4 Experimental setup 16 4.1 Intrinsic Variations 16 4.2 Extrinsic Variations 17 4.3 Control Block 17 4.4 Logic Block 17 4.5 Experimental parameters 19 Chapter 5 Experimental Results 20 5.1 Results at the TT 22 5.2 Result at the FF 22 5.3 Results at the SS 22 5.4 Effect on temperature 25U 5.5 Final power savings 26 Chapter 6 Conclusion and future work 29 Bibliography 31Maste

Methods to improve the reliability and resiliency of near/sub-threshold digital circuits

Energy consumption is one of the primary bottlenecks to both large and small scale modern compute platforms. Reducing the operating voltage of digital circuits to voltages where the supply voltage is near or below the threshold of the transistors has recently gained attention as a method to reduce the energy required for computations by as much as 6 times. However, when operating at near/sub-threshold voltages (where the supply voltage is near or below the threshold of the transistors), imperfections in transistor manufacturing, changes in temperature, and other difficult-to-predict factors cause wide variations in the timing of Complementary Metal-Oxide Semiconductor (CMOS) circuits due to an increased sensitivity at lower voltages. These increased variations result in poor aggregate performance and cause increased rates of error occurrence in computation. This work introduces several new methods to improve the reliability of near/sub-threshold circuits. The first is a design automation technique that is used to aid in low-voltage digital standard cell synthesis. Second, two circuit-level techniques are also introduced that aim to improve the reliability and resiliency of digital circuits by means of completion/error detection. These techniques are shown to improve speed and lower energy consumption at low overheads compared to previous methods. Most importantly, these circuit-level methods are specifically designed to operate at low voltages and can themselves tolerate variations and operation in harsh environments. Finally, a test-chip prototype designed in 65nm-CMOS demonstrates the practicality and feasibility of a proposed current sensing error detector

An asynchronous DES in contactless smartcard.

Siu, Pui-Lam.Thesis submitted in: August 2003.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 104-109).Abstracts in English and Chinese.list of figures --- p.5list of tables --- p.7acknowledgements --- p.8abstract --- p.9Chapter 1. --- introduction --- p.12Chapter 1.1 --- Smart Card --- p.12Chapter 1.1.1 --- What is a smart card? --- p.12Chapter 1.1.2 --- How is a smart card different from the magnetic stripe card that I carry in my wallet? --- p.13Chapter 1.1.3 --- Why are interoperability and enforced standards crucial to widespread adoption of smart cards? --- p.13Chapter 1.1.4 --- Contact vs Contactless --- p.14Chapter 1.1.5 --- How secure and confidential contactless smart cards are? --- p.14Chapter 1.1.6 --- Contactless Smart Card Application Contactless smart cards are widely used in commercial fields as stored-value and secure storage cards --- p.14Chapter 1.1.7 --- What are the major benefits that Contactless smart cards offer to consumers? --- p.16Chapter 1.2 --- Design Motivation --- p.16Chapter 1.3 --- RF Part Interface --- p.17Chapter 1.4 --- Potential Advantages of Using Asynchronous Circuit --- p.19Chapter 1.5 --- Design Methodology for Asynchronous Circuit --- p.23Chapter 1.5.1 --- Difficulty and limitation of asynchronous design --- p.27Chapter 1.5.2 --- Asynchronous pipeline --- p.28Chapter 2. --- background theory --- p.32Chapter 2.1 --- Description of DES --- p.32Chapter 2.1.1 --- Outline of the Algorithm --- p.33Chapter 2.1.2 --- Initial Permutation --- p.35Chapter 2.1.3 --- Key Transformation --- p.35Chapter 2.1.4 --- Expansion Permutation --- p.37Chapter 2.1.5 --- S-box Substitution --- p.38Chapter 2.1.6 --- P-Box Permutation --- p.41Chapter 2.1.7 --- Final Permutation --- p.42Chapter 2.1.8 --- Decrypting DES --- p.43Chapter 2.1.9 --- Security of DES --- p.43Chapter 2.1.10 --- Weak Keys --- p.43Chapter 2.1.11 --- Algebraic Structure --- p.46Chapter 2.1.12 --- Key Length --- p.46Chapter 2.1.13 --- Number of Rounds --- p.48Chapter 2.1.14 --- Design of the S-Boxes --- p.48Chapter 3. --- rf part --- p.50Chapter 3.1 --- Power On --- p.51Chapter 3.2 --- Power Induction --- p.52Chapter 3.3 --- Limiter and Regulator --- p.54Chapter 3.4 --- Demodulation --- p.56Chapter 3.5 --- Modulation --- p.57Chapter 4. --- asynchronous circuit theory --- p.58Chapter 4.1 --- Potential Problem of Classical Asynchronous Pipeline --- p.58Chapter 4.2 --- The New Handshake Cell --- p.58Chapter 4.3 --- The Modified Asynchronous Pipeline Architecture --- p.60Chapter 4.4 --- Asynchronous Circuit Comparison --- p.65Chapter 5 --- implementation --- p.67Chapter 5.1 --- DES Implementation --- p.67Chapter 5.1.1 --- Power estimation of the asynchronous DES --- p.70Chapter 5.1.2 --- Modified Circuit --- p.73Type One --- p.73Type two --- p.76Chapter 5.1.3 --- Interface --- p.79Chapter 5.1.4 --- Shift Unit --- p.80Chapter 5.1.5 --- Multiplexer Unit --- p.82Chapter 5.1.6 --- Compression Unit --- p.83Chapter 5.1.7 --- Expansion Unit --- p.84Chapter 5.1.8 --- Xor Unit --- p.85Chapter 5.1.9 --- S_box Unit --- p.86Chapter 5.1.10 --- P-box unit --- p.88Chapter 5.1.11 --- Latch unit --- p.89Chapter 5.1.12 --- Transmission Unit --- p.90Chapter 5.2 --- Floor Plan Design --- p.90Chapter 6. --- result and discussion --- p.93Chapter 6.1 --- Simulation Result --- p.93Chapter 6.2 --- Measurement --- p.97Chapter 6.3 --- Comparison --- p.101Chapter 6.4 --- Conclusion --- p.101Chapter 7. --- reference --- p.104Chapter 8. --- appendix --- p.110Chapter 8.1 --- RF Part Implementation --- p.110Chapter 8.1.1 --- Full wave rectifying circuit --- p.110Chapter 8.1.2 --- "Limiting Circuit," --- p.111Chapter 8.1.3 --- Regulator circuit --- p.113Chapter 8.1.4 --- Demodulation circuit --- p.113Chapter 8.1.5 --- Simulation of the RF part --- p.115Chapter 8.2 --- New Technology for Designing a RF Interface --- p.117Chapter 8.2 --- Block Diagrams --- p.11