Design and implementation of a suitable core for on-chip long-term verification

Traditional on-chip and off-chip logic analyzers present important shortcomings when used for the long-term verification of industrial embedded systems, forcing the designer to implement ad-hoc verification solutions. This contribution presents a suitable solution for long-term verification of FPGAbased designs consisting on a verification core that uses the Picoblaze microcontroller, dedicated logic and a serial port communication in order to monitor the internal signals of the system in a continuous way. The core design focuses on low resource requirements and reusability and has been successfully applied to the verification of a real industrial synchronization platform showing remarkable advantages over commercial onchip solutions like Xilinx’s ChipScope Pro.Ministerio de Educación y Cultura TEC2007-61802/MIC (HIPERMinisterio de Educación y Cultura PROFIT-MITC SEPIC TSI-020100-2008-25

SCM : Secure Code Memory Architecture

An increasing number of applications implemented on a SoC (System-on-chip) require security features. This work addresses the issue of protecting the integrity of code and read-only data that is stored in memory. To this end, we propose a new architecture called SCM, which works as a standalone IP core in a SoC. To the best of our knowledge, there exist no architectural elements similar to SCM that offer the same strict security guarantees while, at the same time, not requiring any modifications to other IP cores in its SoC design. In addition, SCM has the flexibility to select the parts of the software to be protected, which eases the integration of our solution with existing software. The evaluation of SCM was done on the Zynq platform which features an ARM processor and an FPGA. The design was evaluated by executing a number of different benchmarks from memory protected by SCM, and we found that it introduces minimal overhead to the system

VLSI Architecture and Design

Integrated circuit technology is rapidly approaching a state where feature sizes of one micron or less are tractable. Chip sizes are increasing slowly. These two developments result in considerably increased complexity in chip design. The physical characteristics of integrated circuit technology are also changing. The cost of communication will be dominating making new architectures and algorithms both feasible and desirable. A large number of processors on a single chip will be possible. The cost of communication will make designs enforcing locality superior to other types of designs. Scaling down feature sizes results in increase of the delay that wires introduce. The delay even of metal wires will become significant. Time tends to be a local property which will make the design of globally synchronous systems more difficult. Self-timed systems will eventually become a necessity. With the chip complexity measured in terms of logic devices increasing by more than an order of magnitude over the next few years the importance of efficient design methodologies and tools become crucial. Hierarchical and structured design are ways of dealing with the complexity of chip design. Structered design focuses on the information flow and enforces a high degree of regularity. Both hierarchical and structured design encourage the use of cell libraries. The geometry of the cells in such libraries should be parameterized so that for instance cells can adjust there size to neighboring cells and make the proper interconnection. Cells with this quality can be used as a basis for "Silicon Compilers"

Transparent code authentication at the processor level

The authors present a lightweight authentication mechanism that verifies the authenticity of code and thereby addresses the virus and malicious code problems at the hardware level eliminating the need for trusted extensions in the operating system. The technique proposed tightly integrates the authentication mechanism into the processor core. The authentication latency is hidden behind the memory access latency, thereby allowing seamless on-the-fly authentication of instructions. In addition, the proposed authentication method supports seamless encryption of code (and static data). Consequently, while providing the software users with assurance for authenticity of programs executing on their hardware, the proposed technique also protects the software manufacturers’ intellectual property through encryption. The performance analysis shows that, under mild assumptions, the presented technique introduces negligible overhead for even moderate cache sizes

A FPGA system for QRS complex detection based on Integer Wavelet Transform

Due to complexity of their mathematical computation, many QRS detectors are implemented in software and cannot operate in real time. The paper presents a real-time hardware based solution for this task. To filter ECG signal and to extract QRS complex it employs the Integer Wavelet Transform. The system includes several components and is incorporated in a single FPGA chip what makes it suitable for direct embedding in medical instruments or wearable health care devices. It has sufficient accuracy (about 95%), showing remarkable noise immunity and low cost. Additionally, each system component is composed of several identical blocks/cells what makes the design highly generic. The capacity of today existing FPGAs allows even dozens of detectors to be placed in a single chip. After the theoretical introduction of wavelets and the review of their application in QRS detection, it will be shown how some basic wavelets can be optimized for easy hardware implementation. For this purpose the migration to the integer arithmetic and additional simplifications in calculations has to be done. Further, the system architecture will be presented with the demonstrations in both, software simulation and real testing. At the end, the working performances and preliminary results will be outlined and discussed. The same principle can be applied with other signals where the hardware implementation of wavelet transform can be of benefit

IEEE Standard 1500 Compliance Verification for Embedded Cores

Core-based design and reuse are the two key elements for an efficient system-on-chip (SoC) development. Unfortunately, they also introduce new challenges in SoC testing, such as core test reuse and the need of a common test infrastructure working with cores originating from different vendors. The IEEE 1500 Standard for Embedded Core Testing addresses these issues by proposing a flexible hardware test wrapper architecture for embedded cores, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Several intellectual property providers have already announced IEEE Standard 1500 compliance in both existing and future design blocks. In this paper, we address the problem of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE Standard 1500. This step is mandatory to fully trust the wrapper functionalities in applying the test sequences to the core. We present a systematic methodology to build a verification framework for IEEE Standard 1500 compliant cores, allowing core providers and/or integrators to verify the compliance of their products (sold or purchased) to the standar

Long-term on-chip verification of systems with logical events scattered in time

Traditional on-chip and off-chip logic analyzers present important shortcomings when used for the longterm verification of industrial embedded systems, forcing the designer to implement ad hoc verification solutions. This paper introduces a suitable solution for long-term verification of FPGA-based designs consisting of a verification core that uses the PicoBlaze microcontroller, dedicated logic and a serial port communication in order to monitor the internal signals of the system in a continuous way. The core design focuses on low resource requirements and has been successfully applied to the verification of a real industrial synchronization platform showing remarkable advantages over commercial on-chip solutions like Xilinx’s ChipScope Pro. Moreover, in order to improve the reusability of this core a software tool has been developed to automatically include the verification core in any specific system.Ministerio de Educación y Ciencia TEC2007-61802/MI

Compressed Passive Macromodeling

This paper presents an approach for the extraction of passive macromodels of large-scale interconnects from their frequency-domain scattering responses. Here, large scale is intended both in terms of number of electrical ports and required dynamic model order. For such structures, standard approaches based on rational approximation via vector fitting and passivity enforcement via model perturbation may fail because of excessive computational requirements, both in terms of memory size and runtime. Our approach addresses this complexity by first reducing the redundancy in the raw scattering responses through a projection and approximation process based on a truncated singular value decomposition. Then we formulate a compressed rational fitting and passivity enforcement framework which is able to obtain speedup factors up to 2 and 3 orders of magnitude with respect to standard approaches, with full control over the approximation errors. Numerical results on a large set of benchmark cases demonstrate the effectiveness of the proposed techniqu