Channelization for Multi-Standard Software-Defined Radio Base Stations

As the number of radio standards increase and spectrum resources come under more pressure, it becomes ever less efficient to reserve bands of spectrum for exclusive use by a single radio standard. Therefore, this work focuses on channelization structures compatible with spectrum sharing among multiple wireless standards and dynamic spectrum allocation in particular. A channelizer extracts independent communication channels from a wideband signal, and is one of the most computationally expensive components in a communications receiver. This work specifically focuses on non-uniform channelizers suitable for multi-standard Software-Defined Radio (SDR) base stations in general and public mobile radio base stations in particular. A comprehensive evaluation of non-uniform channelizers (existing and developed during the course of this work) shows that parallel and recombined variants of the Generalised Discrete Fourier Transform Modulated Filter Bank (GDFT-FB) represent the best trade-off between computational load and flexibility for dynamic spectrum allocation. Nevertheless, for base station applications (with many channels) very high filter orders may be required, making the channelizers difficult to physically implement. To mitigate this problem, multi-stage filtering techniques are applied to the GDFT-FB. It is shown that these multi-stage designs can significantly reduce the filter orders and number of operations required by the GDFT-FB. An alternative approach, applying frequency response masking techniques to the GDFT-FB prototype filter design, leads to even bigger reductions in the number of coefficients, but computational load is only reduced for oversampled configurations and then not as much as for the multi-stage designs. Both techniques render the implementation of GDFT-FB based non-uniform channelizers more practical. Finally, channelization solutions for some real-world spectrum sharing use cases are developed before some final physical implementation issues are considered

Cognitive Radio-Modulation and Demodulation

The reconfigurability in Cognitive Radio (CR) facilitates to dynamically change its parameters for the efficient spectrum utilization. The motivation behind the study of cognitive radio is that the number of different radio signals can be handled without using extra circuitry, i.e., reusing identical hardware with the change in the software will reduce time to market, development cost, and upgrade infrastructure. Software Defined Radio (SDR) is an enabling technology for Cognitive Radio (CR); therefore, it emphasizes on SDR unique features, characteristics, and basics concepts that are required to understand operation of SDR. SDR allows service providers to upgrade infrastructure without unreasonable cost. Modulation techniques play a vital role in any communication systems such as cable modems, DSL modems, CDMA, 4G, Wi-Fi, and WIMAX; thus, it emphasizes on implementation of modulation techniques using SDR Generic hardware, which is operated by Open Source software called GNU Radio. Implementation of various analog and digital modulation techniques using the GNU Radio provides a way for developing advanced wireless communication system. GNU Radio software is a highly flexible signal processing platform, which makes it easy and reduces time to implement different modulation techniques with appropriate script

Portable Waveform Development for Software Defined Radios

This work focuses on the question: "How can we build waveforms that can be moved from one platform to another?\u27\u27 Therefore an approach based on the Model Driven Architecture was evaluated. Furthermore, a proof of concept is given with the port of a TETRA waveform from a USRP platform to an SFF SDR platform

BASEBAND RADIO MODEM DESIGN USING GRAPHICS PROCESSING UNITS

A modern radio or wireless communications transceiver is programmed via software and firmware to change its functionalities at the baseband. However, the actual implementation of the radio circuits relies on dedicated hardware, and the design and implementation of such devices are time consuming and challenging. Due to the need for real-time operation, dedicated hardware is preferred in order to meet stringent requirements on throughput and latency. With increasing need for higher throughput and shorter latency, while supporting increasing bandwidth across a fragmented spectrum, dedicated subsystems are developed in order to service individual frequency bands and specifications. Such a dedicated-hardware-intensive approach leads to high resource costs, including costs due to multiple instantiations of mixers, filters, and samplers. Such increases in hardware requirements in turn increases device size, power consumption, weight, and financial cost. If it can meet the required real-time constraints, a more flexible and reconfigurable design approach, such as a software-based solution, is often more desirable over a dedicated hardware solution. However, significant challenges must be overcome in order to meet constraints on throughput and latency while servicing different frequency bands and bandwidths. Graphics processing unit (GPU) technology provides a promising class of platforms for addressing these challenges. GPUs, which were originally designed for rendering images and video sequences, have been adapted as general purpose high-throughput computation engines for a wide variety of application areas beyond their original target domains. Linear algebra and signal processing acceleration are examples of such application areas. In this thesis, we apply GPUs as software-based, baseband radios and demonstrate novel, software-based implementations of key subsystems in modern wireless transceivers. In our work, we develop novel implementation techniques that allow communication system designers to use GPUs as accelerators for baseband processing functions, including real-time filtering and signal transformations. More specifically, we apply GPUs to accelerate several computationally-intensive, frontend radio subsystems, including filtering, signal mixing, sample rate conversion, and synchronization. These are critical subsystems that must operate in real-time to reliably receive waveforms. The contributions of this thesis can be broadly organized into 3 major areas: (1) channelization, (2) arbitrary resampling, and (3) synchronization. 1. Channelization: a wideband signal is shared between different users and channels, and a channelizer is used to separate the components of the shared signal in the different channels. A channelizer is often used as a pre-processing step in selecting a specific channel-of-interest. A typical channelization process involves signal conversion, resampling, and filtering to reject adjacent channels. We investigate GPU acceleration for a particularly efficient form of channelizer called a polyphase filterbank channelizer, and demonstrate a real-time implementation of our novel channelizer design. 2. Arbitrary resampling: following a channelization process, a signal is often resampled to at least twice the data rate in order to further condition the signal. Since different communication standards require different resampling ratios, it is desirable for a resampling subsystem to support a variety of different ratios. We investigate optimized, GPU-based methods for resampling using polyphase filter structures that are mapped efficiently into GPU hardware. We investigate these GPU implementation techniques in the context of interpolation (integer-factor increases in sampling rate), decimation (integer-factor decreases in sampling rate), and rational resampling. Finally, we demonstrate an efficient implementation of arbitrary resampling using GPUs. This implementation exploits specialized hardware units within the GPU to enable efficient and accurate resampling processes involving arbitrary changes in sample rate. 3. Synchronization: incoming signals in a wireless communications transceiver must be synchronized in order to recover the transmitted data properly from complex channel effects such as thermal noise, fading, and multipath propagation. We investigate timing recovery in GPUs to accelerate the most computationally intensive part of the synchronization process, and correctly align the incoming data symbols in the receiver. Furthermore, we implement fully-parallel timing error detection to accelerate maximum likelihood estimation

Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers

In wireless communication industry, the convergence of stand-alone, single application transceiver IC’s into scalable, programmable and platform based transceiver ICs, has led to the possibility to create sophisticated mobile devices within a limited volume. These multi-standard (multi-mode), MIMO, SDR and cognitive radios, ask for more adaptability and flexibility on every abstraction level of the transceiver. The adaptability and flexibility of the receive paths require a digitized receiver architecture in which most of the adaptability and flexibility is shifted in the digital domain. This trend to ask for more adaptability and flexibility, but also more performance, higher efficiency and an increasing functionality per volume, has a major impact on the IP blocks such systems are built with. At the same time the increasing requirement for more digital processing in the same volume and for the same power has led to mainstream CMOS feature size scaling, leading to smaller, faster and more efficient transistors, optimized to increase processing efficiency per volume (smaller area, lower power consumption, faster digital processing). As wireless receivers is a comparably small market compared to digital processors, the receivers also have to be designed in a digitally optimized technology, as the processor and transceiver are on the same chip to reduce device volume. This asks for a generalized approach, which maps application requirements of complex systems (such as wireless receivers) on the advantages these digitally optimized technologies bring. First, the application trends are gathered in five quality indicators being: (algorithmic) accuracy, robustness, flexibility, efficiency, and emission, of which the last one is not further analyzed in this thesis. Secondly, using the quality indicators, it is identified that by introducing (or increasing) digitization at every abstraction level of a system, the advantages of modern digitally optimized technologies can be exploited. For a system on a chip, these abstraction levels are: system/application level, analog IP architecture level, circuit topology level and layout level. In this thesis, the quality indicators together with the digitization at different abstraction levels are applied to S¿ modulators. S¿ modulator performance properties are categorized into the proposed quality indicators. Next, it is identified what determines the accuracy, robustness, flexibility and efficiency of a S¿ modulator. Important modulator performance parameters, design parameter relations, and performance-cost relations are derived. Finally, several implementations are presented, which are designed using the found relations. At least one implementation example is shown for each level of digitization. At system level, a flexible (N)ZIF receiver architecture is digitized by shifting the ADC closer to the antenna, reducing the amount of analog signal conditioning required in front of the ADC, and shifting the re-configurability of such a receiver into the digital domain as much as possible. Being closer to the antenna, and because of the increased receiver flexibility, a high performance, multi-mode ADC is required. In this thesis, it is proven that such multi-mode ADCs can be made at low area and power consumption. At analog IP architecture level, a smarter S¿ modulator architecture is found, which combines the advantages of 1-bit and multi-bit modulators. The analog loop filter is partly digitized, and analog circuit blocks are replaced by a digital filter, leading to an area and power efficient design, which above all is very portable, and has the potential to become a good candidate for the ADC in multimode receivers. At circuit and layout level, analog circuits are designed in the same way as digital circuits are. Analog IP blocks are split up in analog unit cells, which are put in a library. For each analog unit cell, a p-cell layout view is created. Once such a library is available, different IP blocks can be created using the same unit cells and using the automatic routing tools normally used for digital circuits. The library of unit cells can be ported to a next technology very quickly, as the unit cells are very simple circuits, increasing portability of IP blocks made with these unit cells. In this thesis, several modulators are presented that are designed using this digital design methodology. A high clock frequency in the giga-hertz range is used to test technology speed. The presented modulators have a small area and low power consumption. A modulator is ported from a 65nm to a 45nm technology in one month without making changes to the unit cells, or IP architecture, proving that this design methodology leads to very portable designs. The generalized system property categorization in quality indicators, and the digitization at different levels of system design, is named the digital design methodology. In this thesis this methodology is successfully applied to S¿ modulators, leading to high quality, mixed-signal S¿ modulator IP, which is more accurate, more robust, more flexible and/or more efficient

Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers

In wireless communication industry, the convergence of stand-alone, single application transceiver IC’s into scalable, programmable and platform based transceiver ICs, has led to the possibility to create sophisticated mobile devices within a limited volume. These multi-standard (multi-mode), MIMO, SDR and cognitive radios, ask for more adaptability and flexibility on every abstraction level of the transceiver. The adaptability and flexibility of the receive paths require a digitized receiver architecture in which most of the adaptability and flexibility is shifted in the digital domain. This trend to ask for more adaptability and flexibility, but also more performance, higher efficiency and an increasing functionality per volume, has a major impact on the IP blocks such systems are built with. At the same time the increasing requirement for more digital processing in the same volume and for the same power has led to mainstream CMOS feature size scaling, leading to smaller, faster and more efficient transistors, optimized to increase processing efficiency per volume (smaller area, lower power consumption, faster digital processing). As wireless receivers is a comparably small market compared to digital processors, the receivers also have to be designed in a digitally optimized technology, as the processor and transceiver are on the same chip to reduce device volume. This asks for a generalized approach, which maps application requirements of complex systems (such as wireless receivers) on the advantages these digitally optimized technologies bring. First, the application trends are gathered in five quality indicators being: (algorithmic) accuracy, robustness, flexibility, efficiency, and emission, of which the last one is not further analyzed in this thesis. Secondly, using the quality indicators, it is identified that by introducing (or increasing) digitization at every abstraction level of a system, the advantages of modern digitally optimized technologies can be exploited. For a system on a chip, these abstraction levels are: system/application level, analog IP architecture level, circuit topology level and layout level. In this thesis, the quality indicators together with the digitization at different abstraction levels are applied to S¿ modulators. S¿ modulator performance properties are categorized into the proposed quality indicators. Next, it is identified what determines the accuracy, robustness, flexibility and efficiency of a S¿ modulator. Important modulator performance parameters, design parameter relations, and performance-cost relations are derived. Finally, several implementations are presented, which are designed using the found relations. At least one implementation example is shown for each level of digitization. At system level, a flexible (N)ZIF receiver architecture is digitized by shifting the ADC closer to the antenna, reducing the amount of analog signal conditioning required in front of the ADC, and shifting the re-configurability of such a receiver into the digital domain as much as possible. Being closer to the antenna, and because of the increased receiver flexibility, a high performance, multi-mode ADC is required. In this thesis, it is proven that such multi-mode ADCs can be made at low area and power consumption. At analog IP architecture level, a smarter S¿ modulator architecture is found, which combines the advantages of 1-bit and multi-bit modulators. The analog loop filter is partly digitized, and analog circuit blocks are replaced by a digital filter, leading to an area and power efficient design, which above all is very portable, and has the potential to become a good candidate for the ADC in multimode receivers. At circuit and layout level, analog circuits are designed in the same way as digital circuits are. Analog IP blocks are split up in analog unit cells, which are put in a library. For each analog unit cell, a p-cell layout view is created. Once such a library is available, different IP blocks can be created using the same unit cells and using the automatic routing tools normally used for digital circuits. The library of unit cells can be ported to a next technology very quickly, as the unit cells are very simple circuits, increasing portability of IP blocks made with these unit cells. In this thesis, several modulators are presented that are designed using this digital design methodology. A high clock frequency in the giga-hertz range is used to test technology speed. The presented modulators have a small area and low power consumption. A modulator is ported from a 65nm to a 45nm technology in one month without making changes to the unit cells, or IP architecture, proving that this design methodology leads to very portable designs. The generalized system property categorization in quality indicators, and the digitization at different levels of system design, is named the digital design methodology. In this thesis this methodology is successfully applied to S¿ modulators, leading to high quality, mixed-signal S¿ modulator IP, which is more accurate, more robust, more flexible and/or more efficient