Design and implementation of a low power spike detection processor for 128-channel spike sorting microsystem

It is impractical to apply a general spike sorting algo-rithm for every subject because of the individual character-istics of brain signal. Furthermore, extracting more neural activities for higher accuracy of spike sorting requires more input electrodes as well as large power consumption and chip area. Therefore, several practical constraints are considered in this work when implementing a programmable spike sorting hardware with large number of input channels. In this paper, we provide a 128-channel spike detection processor for spike sorting microsystem without compromise of the power effi-ciency. This chip consumes only 87.02uW and 9.7uW/mm2 of power density, fabricated with 90nm low-leakage CMOS process