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2 research outputs found
Design And Performance Of A Coherent Cache For Parallel Logic Programming Architectures
Author
Publication venue
'Institute of Electrical and Electronics Engineers (IEEE)'
Publication date
01/01/1989
Field of study
No full text
Crossref
Design and performance of a coherent cache for parallel logic programming architectures
Author
A. Goto
A. Goto
+9Â more
A. Matsumoto
E. Lusk
E. Tick
Kimura Y.
M. Sato
Nakashima H.
T. Chikayama
Ueda K.
Warren D. H. D.
Publication venue
'Association for Computing Machinery (ACM)'
Publication date
Field of study
No full text
Crossref
No full text
No full text
