Design and Optimization of Test Solutions for Core-based System-On-Chip Benchmark Circuits Using Genetic Algorithm

Abstract- The increased usage of embedded pre-designed reusable cores necessitates a core-based test strategy in which cores are tested as separate entities. Test application time is a major issue in System-on-Chip Testing (SOC). Pre-designed cores and reusable modules are popularly used in the design of large and complex systems. As the complexity of system increases, the test application time also significantly increases. Available techniques for testing of core-based SOC do not provide a systematic means of compact test solutions. The test application time must be minimized to transport test data to and from the cores. In this paper, we present a Genetic Algorithm (GA)-based approach to optimize the test vectors for globally asynchronous locally synchronous SOC Benchmark Circuits. This approach provides optimal results comparable to other methods of similar problems. Based on our experiments, the test results for four ITC-02 SOC Test Benchmark circuits are presented. The results of GA-based approach are shown to be superior to the heuristic approaches proposed in the literature