Designing with RoBs for High Performance VLIW Architecture

VLIW architecture has become widespread due to the combined bene?ts of simple hardware and compiler extracted instruction level parallelism. The VLIW instruction set architecture and its hardware implementation is tightly coupled and a novel simultaneous multithreading VLIW architecture with dynamic dispatch mechanism which uses RoBs complex logic to maximize ILP has been proposed. Since the resulting dynamic instruction schedule of many applications seldom changes, it is reasonable to store and reuse the schedule instead of reconstructing it each time. The new VLIW architecture shows that it can effectively increase the processor efficiency which improves the performance

Design and Analysis of a Low Power VLIW DSP Core

Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a power efficient system, architecture design, compiler optimization, as well as user evaluation must be employed in a unified framework. This paper presents an architecture-level power/performance simulator for a VLIW DSP processor core. Relying on parameterized power models and cycle accurate simulation, it provides fast and accurate power estimation for architecture exploration. Furthermore, the proposed modeling methodology can be used with minimal changes in the evaluation of other VLIW processor cores or for characterizing the efficiency of compiler-driven power efficient transformations. 1