1 research outputs found
Partial Reconfiguration for Design Optimization
FPGA designers have traditionally shared a similar design methodology with
ASIC designers. Most notably, at design time, FPGA designers commit to a fixed
allocation of logic resources to modules in a design. At runtime, some of the
occupied resources could be left idle or under-utilized due to hard-to-avoid
sources of inefficiencies (e.g., operation dependencies). With partial
reconfiguration (PR), FPGA resources can be re-allocated over time. Therefore,
using PR, a designer can attempt to reduce idleness and under-utilization with
better area-time scheduling.
In this paper, we explain when, how, and why PR-style designs can improve
over the performance-area Pareto front of ASIC-style designs (without PR). We
first introduce the concept of area-time volume to explain why PR-style designs
can improve upon ASIC-style designs. We identify resource under-utilization as
an opportunity that can be exploited by PR-style designs. We then present a
first-order analytical model to help a designer decide if a PR-style design can
be beneficial. When it is the case, the model points to the most suitable PR
execution strategy and provides an estimate of the improvement. The model is
validated in three case studies