Delay Performance of High-Speed Packet Switches with Low Speedup

Absuoct-The s p d q of a milch is lho factor by which the "Itch, and hence the memory used 111 the switch, mns faster compared to the llnc rate. lo higbspd switches, Uno nb am already toorhlog Umitl at which memory cm operate. In this arraa~, it b wry Important far a switch to mn at U low a spltdop as parriblr In the puf, U hu k o rho- that 1WX throoghput cm be achieved far my admirsiblr triffir for an lnpnt Queued OQ) switch 111, 121 at speedup one. This gives Anite ivrnge delays but dui not guarantee cor,fml on packet drbys. In 131, amlhon show that a Comblned Inpml Ootpnt Queued (CIOQ) "Itch em emulate perfectly an Oogol Queued (OQ) switch at a speedup of 2 and, tho,, eoob01 the packet delays. Thb moll- terms of average delay. v~trrtheItudy~fpoulbilityafobt.ioin~drl~yoa~lml~tsprrdupInsIb~a 2. To guarante optimal control of delays for a grocral dau of traffic,.I rho- in 131, &up 2 Is necessary. Heme, to obWo ronml of ddam at lower speedup. we need to restrict the dmrr of arrival traffics. Io thii paper. we study the speedup requirement for a cius of admirrihk traffic, which we will denote as (I, nF)-reguiated tmffic, with p.rm"m n md F. We obtain the necessary speedup for this elarr of traffic. Further, we pmient a general dm of algorithms worldng at the necessary @ups and thus providing bounded Mays