Decentralized BIST for 1149.1 and 1149.5 Based Interconnects

This paper presents a decentralized BIST methodology for system level interconnects. For 3-state nets, we interleave pseudorandom counting sequences (PCS) and walking sequences to avoid the conflict among multiple drivers of a net. For multiple scan chains, each chain is applied with a particular window of the PCS to ensure the distinctness of every test vector and 100# stuck-at and short faults coverage for nets across scan chains and/or board boundaries. The synchronization of chains of different lengths is handled gracefully by inserting a preamble to make all the chains the same length