Data-flow Assisted Behavioral Partitioning for Embedded Systems

In this paper we present a novel compiler-directed approach to system-level partitioning for a given description of system functionality in a hardware description language (HDL). The algorithm is based on a definition-use analysis of the storage in the system model to ensure that the resulting portions can be implemented in a loosely-coupled multi-rate execution model with minimal synchronization between the portions. The cost of the hardware-software interface, in terms of amount of buffering required, is computed accurately as a part of the partitioning cost function using a data-flow reaching analysis. The proposed algorithm has been implemented and experimental results show up to 65% improvement in buffer sizes over the min-cut partitioning algorithm