Transient fault behavior in a microprocessor: A case study

An experimental analysis is described which studies the susceptibility of a microprocessor based jet engine controller to upsets caused by current and voltage transients. A design automation environment which allows the run time injection of transients and the tracing from their impact device to the pin level is described. The resulting error data are categorized by the charge levels of the injected transients by location and by their potential to cause logic upsets, latched errors, and pin errors. The results show a 3 picoCouloumb threshold, below which the transients have little impact. An Arithmetic and Logic Unit transient is most likely to result in logic upsets and pin errors (i.e., impact the external environment). The transients in the countdown unit are potentially serious since they can result in latched errors, thus causing latent faults. Suggestions to protect the processor against these errors, by incorporating internal error detection and transient suppression techniques, are also made

Robust DC and efficient time-domain fast fault simulation

Purpose – Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation one simulates all situations. Normally this leads to a large list of simulations in which for each defect a steady-state (DC) solution is determined followed by a transient simulation. We improve the robustness and the e¿iciency of these simulations. Design/methodology/approach – Determining the DC solution can be very hard. For this we present an adaptive time domain source stepping procedure that can deal with controlled sources. The method can easily be combined with existing pseudo-transient procedures. The method is robust and e¿cient. In the subsequent transient simulation the solution of a fault is compared to a golden, fault-free, solution. A strategy is developed to e¿ciently simulate the faulty solutions until their moment of detection. Finding – We fully exploit the hierarchical structure the circuit in the simulation process to bypass parts of the circuit that appear to be una¿ected by the fault. Accurate prediction and e¿cient solution procedures lead to fast fault simulation. Originality/value – Our fast fault simulation helps to store a database with detectable deviations for each fault. If such a detectable output "matches" a result of a product that has been returned because of malfunctioning it helps to identify the subcircuit that may contain the real fault. One aims to detect as much as possible candidate faults. Because of the many options the simulations must be very e¿cient

Robust DC and efficient time-domain fast fault simulation

Purpose – Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation one simulates all situations. Normally this leads to a large list of simulations in which for each defect a steady-state (DC) solution is determined followed by a transient simulation. We improve the robustness and the e¿iciency of these simulations. Design/methodology/approach – Determining the DC solution can be very hard. For this we present an adaptive time domain source stepping procedure that can deal with controlled sources. The method can easily be combined with existing pseudo-transient procedures. The method is robust and e¿cient. In the subsequent transient simulation the solution of a fault is compared to a golden, fault-free, solution. A strategy is developed to e¿ciently simulate the faulty solutions until their moment of detection. Finding – We fully exploit the hierarchical structure the circuit in the simulation process to bypass parts of the circuit that appear to be una¿ected by the fault. Accurate prediction and e¿cient solution procedures lead to fast fault simulation. Originality/value – Our fast fault simulation helps to store a database with detectable deviations for each fault. If such a detectable output "matches" a result of a product that has been returned because of malfunctioning it helps to identify the subcircuit that may contain the real fault. One aims to detect as much as possible candidate faults. Because of the many options the simulations must be very e¿cient

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Since the last century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The ISO 26262 standard for functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardization of defect modeling and injection mainly focused on digital circuits and, in a minor part, on analog ones. An initial attempt is being made with the IEEE P2427 draft standard that started to give a structured and formal organization to the analog testing field. Various methods have been proposed in the literature to speed up the fault simulation of the defect universe for an analog circuit. A more limited number of papers seek to reduce the overall simulation time by reducing the number of defects to be simulated. This literature survey describes the state-of-the-art of analog defect injection and fault simulation methods. The survey is based on the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) methodological flow, allowing for a systematic and complete literature survey. Each selected paper has been categorized and presented to provide an overview of all the available approaches. In addition, the limitations of the various approaches are discussed by showing possible future directions

State Space Modeling of Smart PV Inverter as STATCOM (PV-STATCOM) for Voltage Control in a Distribution System

The grid integration of photovoltaic (PV) systems in distribution networks is facing challenges such as transient changes in voltage due to fluctuations in generated real power and tripping of PV systems. Smart PV inverters with functions such as dynamic reactive current injection and low voltage ride through are available to mitigate these challenges. This thesis shows that a better stable performance can be obtained if these functions are implemented using the novel patent-pending technology of PV system as a dynamic reactive power compensator (PV-STATCOM). A linearized state space model of PV-STATCOM is developed to show the benefits of PV-STATCOM controls over Smart PV inverter controls in the presence of control system interaction between dc-link voltage and point of common coupling voltage controllers. These benefits are further substantiated by comparing the performance of PV-STATCOM and Smart PV inverter to perform voltage control during system disturbances simulated by irradiance changes and faults

Oscillation-based DFT for Second-order Bandpass OTA-C Filters

This document is the Accepted Manuscript version. Under embargo until 6 September 2018. The final publication is available at Springer via https://doi.org/10.1007/s00034-017-0648-9.This paper describes a design for testability technique for second-order bandpass operational transconductance amplifier and capacitor filters using an oscillation-based test topology. The oscillation-based test structure is a vectorless output test strategy easily extendable to built-in self-test. The proposed methodology converts filter under test into a quadrature oscillator using very simple techniques and measures the output frequency. Using feedback loops with nonlinear block, the filter-to-oscillator conversion techniques easily convert the bandpass OTA-C filter into an oscillator. With a minimum number of extra components, the proposed scheme requires a negligible area overhead. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of Tow-Thomas and KHN OTA-C filters. Simulation results in 0.25μm CMOS technology show that the proposed oscillation-based test strategy for OTA-C filters is suitable for catastrophic and parametric faults testing and also effective in detecting single and multiple faults with high fault coverage.Peer reviewedFinal Accepted Versio

Measurements, Models, Systems and Design

531 s.

IMPACT OF INRUSH CURRENTS AND GEOMAGNETICALLY INDUCED CURRENTS ON TRANSFORMER BEHAVIOR

Transformers are the tie-points of electrical power systems. Their protection from power system faults and other innate issues is of prime importance. A few of the issues that are studied in this report are magnetic inrush currents, geomagnetically induced currents in power transformers and Over-excitation. This project develops a novel way of initializing and visualizing the flux linkage in the transformer core for studies on energization inrush currents. In addition, a quasi-DC source for GIC has been developed in order to study the GIC effects on power transformers and a sensitivity analysis has been carried out to understand effects of GIC amplitudes and frequencies on the transformer core. Lastly, a study has been carried out in order to understand Over-excitation effects on transformers. The cases have been simulated in ATP (Alternative Transients Program) using the hybrid transformer model available in the program. The simulation results suggest the models developed are capable of providing an in depth analysis of GIC, inrush currents and over-excitation. Future recommendations include studies on relationship of var absorption and GIC amplitude as well as developing a model for studying controlled switching with residual flux linkage monitoring for minimizing inrush currents