Cut-less Technology Mapping Using Shannon Factor Graph with on-the-fly Size Reduction

The cut-based technology mapping algorithms are computationally expensive as they require cutenumeration, pruning, and computation of local function of cuts and their canonical form. The number of cuts to be enumerated increases exponentially (O(n K )) with the cut size (k) and graph size (n), due to which the design time and storage for storing the cuts become a bottleneck. Therefore, as a solution, we present a new graph data structure, called Shannon Factor Graph (SFG) to facilitate the cut-less technology mapping, thereby eliminating the need of cut-enumeration and its subsequent steps. Besides, we propose an on-the-fly graph size reduction algorithm to minimize the size of the subject graph, which in turn improves the circuit area (gate count) of the target graph. When compared with the cut-based technology mapping approaches using standard benchmarks, proposed methodology reduces the design time by up to 32× and storage requirements by 282×. Subsequently, comparison with Synopsys DC shows that proposed approach has only an average area overhead of 2.6%