Customized Regular Channel Design in FPGAs

FPGAs are one of the essential components in platform-based embedded systems. Such systems are customized and applied only to a limited set of applications. Also some applications are crucial in timing and the FPGA used in the system needs to be customized for such critical applications. The FPGA routing architectures are mostly designed for general-purpose applications. In this paper, we study the problem of customized regular segmentation design in FPGA routing channels. Compared to other segmentation design, mostly based on stochastic model for general programmable architecture, we propose a deterministic approach. We propose an algorithm for segmentation design problem in which each interval is assigned to only one segment (1-Segmentation). We solve the problem of maximum number of incremental track assignment of intervals by raincost network flow technique for 1-Segmentation design. In kSegmentation design each interval is assigned to at most k segments. We prove that the k-Segmentation design problem for one track can be solved optimally. The general K-Segmentation design problem can also be solved by some modifications in our algorithm