Superconducting Heater Cryotron-Based Reconfigurable Logic Towards Cryogenic IC Camouflaging

Superconducting electronics are among the most promising alternatives to conventional CMOS technology thanks to the ultra-fast speed and ultra-high energy efficiency of the superconducting devices. Having a cryogenic control processor is also a crucial requirement for scaling the existing quantum computers up to thousands of qubits. Despite showing outstanding speed and energy efficiency, Josephson junction-based circuits suffer from several challenges such as flux trapping leading to limited scalability, difficulty in driving high impedances, and so on. Three-terminal cryotron devices have been proposed to solve these issues which can drive high impedances (>100 k{\Omega}) and are free from any flux trapping issue. In this work, we develop a reconfigurable logic circuit using a heater cryotron (hTron). In conventional approaches, the number of devices to perform a logic operation typically increases with the number of inputs. However, here, we demonstrate a single hTron device-based logic circuit that can be reconfigured to perform 1-input copy and NOT, 2-input AND and OR, and 3-input majority logic operations by choosing suitable biasing conditions. Consequently, we can perform any processing task with a much smaller number of devices. Also, since we can perform different logic operations with the same circuit (same layout), we can develop a camouflaged system where all the logic gates will have the same layout. Therefore, this proposed circuit will ensure enhanced hardware security against reverse engineering attacks.Comment: 12 pages, 5 figure

Cryogenic Computer Architecture Modeling with Memory-Side Case Studies

Modern computer architectures suffer from lack of architectural innovations, mainly due to the power wall and the memory wall. That is, architectural innovations become infeasible because they can prohibitively increase power consumption and their performance impacts are eventually bounded by slow memory accesses. To address the challenges, making computer systems run at ultra-low temperatures (or cryogenic computer systems) has emerged as a highly promising solution as both power consumption and wire resistivity are expected to significantly reduce at ultra-low temperatures. However, cryogenic computers have not been yet realized as computer architects do not fully understand the behaviors of existing computer systems and their cost effectiveness at such ultra-low temperatures. In this paper, we first develop CryoRAM, a validated computer architecture simulation tool to incorporate cryogenic memory devices. For this work, we focus on 77K temperature (easily achieved by applying low-cost liquid nitrogen), at which modern CMOS devices still reliably operate. We also focus on reducing the temperature of memory devices only as a pilot study prior to building a full cryogenic computer. Next, driven by the modeling tool, we propose our temperature-aware memory device and architecture designs to improve the DRAM access speed by 3.8 times or reduce the power consumption to 9.2%. Finally, we provide three promising case studies using cryogenic memories to significantly improve (1) server performance (up to 2.5 times), (2) server power (down to 6% on average), and (3) datacenter's power cost (by 8.4%). We will release our modeling and simulation tools deliberately implemented on top of only open-source simulators combined, even though some experiments were conducted under industry-confidential environments.N