Cross-Layer Approaches for an Aging-Aware Design Space Exploration for Microprocessors

Abstract-With the continuous scaling of CMOS technologies, maintaining the microprocessor reliability becomes a major design challenge. In particular, accelerated transistor aging is a serious reliability concern, as it considerably reduces the operational system lifetime. To address this issue, in this work cross-layer solutions for aging modeling, simulation and mitigation are proposed, to be able to co-optimize reliability together with the traditional design constraints such as power, performance, and cost. Therefore, the knowledge from several abstraction layers, ranging circuit-to architecture-level, are exploited for cost-effective aging-aware architecture and system design. The comprehensive simulations and experimental analysis performed in this work show the benefits of this approach over state-of-the-art single-layer solutions