Critical Area Computation - A New Approach

In this paper we present a new approach for computing the critical area for shorts in a circuit layout. The critical area calculation is the main computational problem in VLSI yield prediction. The method is based on the concept of Voronoi diagrams and computes the critical area for shorts (for all possible defect radii, assuming square defects) accurately in O(n log n) time, where n is the size of the input. The method is presented for rectilinear layouts and layouts containing edges of slope \Sigma1. As a byproduct we briefly sketch how to speed up the grid method of Wagner and Koren [18]. 1 Introduction The critical area of a VLSI layout is a measure that reflects the sensitivity of the layout to defects occurring during the manufacturing process and it is widely used to predict the yield of a VLSI chip. Yield prediction is essential in today's VLSI manufacturing due to the growing need to control cost. Models for yield estimation are based on the concept of critical area which re..