Analysis and mitigation of dead time harmonics in the single-phase full-bridge PWM converters with repetitive controllers

In order to prevent the power switching devices (e.g., the Insulated-Gate-Bipolar-Transistor, IGBT) from shoot through in voltage source converters during a switching period, the dead time is added either in the hardware driver circuits of the IGBTs or implemented in software in Pulse-Width Modulation (PWM) schemes. Both solutions will contribute to a degradation of the injected current quality. As a consequence, the harmonics induced by the dead time (referred to as "dead time harmonics" hereafter) have to be compensated in order to achieve a satisfactory current quality as required by standards. In this paper, the emission mechanism of dead time harmonics in single-phase PWM inverters is thus presented considering the modulation schemes in details. More importantly, a repetitive controller has been adopted to eliminate the dead time effect in single-phase grid-connected PWM converters. The repetitive controller has been plugged into a proportional resonant-based fundamental current controller so as to mitigate the dead time harmonics and also maintain the control of the fundamental frequency grid current in terms of dynamics. Simulations and experiments are provided, which confirm that the repetitive controller can effectively compensate the dead time harmonics and other low-order distortions, and also it is a simple method without hardware modifications

Assessment of novel power electronic converters for drives applications

Phd ThesisIn the last twenty years, industrial and academic research has produced over one hundred new converter topologies for drives applications. Regrettably, most of the published work has been directed towards a single topology, giving an overall impression of a large number of unconnected, competing techniques. To provide insight into this wide ranging subject area, an overview of converter topologies is presented. Each topology is classified according to its mode of operation and a family tree is derived encompassing all converter types. Selected converters in each class are analysed, simulated and key operational characteristics identified. Issues associated with the practical implementation of analysed topologies are discussed in detail. Of all AC-AC conversion techniques, it is concluded that softswitching converter topologies offer the most attractive alternative to the standard hard switched converter in the power range up to 100kW because of their high performance to cost ratio. Of the softswitching converters, resonant dc-link topologies are shown to produce the poorest output performance although they offer the cheapest solution. Auxiliary pole commutated inverters, on the other hand, can achieve levels of performance approaching those of the hard switched topology while retaining the benefits of softswitching. It is concluded that the auxiliary commutated resonant pole inverter (ACPI) topology offers the greatest potential for exploitation in spite of its relatively high capital cost. Experimental results are presented for a 20kW hard switched inverter and an equivalent 20kW ACPI. In each case the converter controller is implanted using a digital signal processor. For the ACPI, a new control scheme, which eliminates the need for switch current and voltage sensors, is implemented. Results show that the ACPI produces lower overall losses when compared to its hardswitching counterpart. In addition, device voltage stress, output dv/dt and levels of high frequency output harmonics are all reduced. Finally, it is concluded that modularisation of the active devices, optimisation of semiconductor design and a reduction in the number of additional sensors through the use of novel control methods, such as those presented, will all play a part in the realisation of an economically viable system.Research Committee of the University of Newcastle upon Tyn

Phase Locking Authentication for Scan Architecture

Scan design is a widely used Design for Testability (DfT) approach for digital circuits. It provides a high level of controllability and observability resulting in a high fault coverage. To achieve a high level of testability, scan architecture must provide access to the internal nodes of the circuit-under-test (CUT). This access however leads to vulnerability in the security of the CUT. If an unrestricted access is provided through a scan architecture, unlimited test vectors can be applied to the CUT and its responses can be captured. Such an unrestricted access to the CUT can potentially undermine the security of the critical information stored in the CUT. There is a need to secure scan architecture to prevent hardware attacks however a secure solution may limit the CUT testability. There is a trade-off between security and testability, therefore, a secure scan architecture without hindering its controllability and observability is required. Three solutions to secure scan architecture have been proposed in this thesis. In the first method, the tester is authenticated and the number of authentication attempts has been limited. In the second method, a Phase Locked Loop (PLL) is utilized to secure scan architecture. In the third method, the scan architecture is secured through a clock and data recovery (CDR) technique. This is a manuscript based thesis and the results of this study have been published in two conference proceedings. The latest results have also been prepared as an article for submission to a high rank conference

Analysis of two level and three level inverters

The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as inverter. Inverters can be broadly classified into single level inverter and multilevel inverter. Multilevel inverter as compared to single level inverters have advantages like minimum harmonic distortion, reduced MI/RFI generation and can operate on several voltage levels. A multi-stage inverter is being utilized for multipurpose applications, such as active power filters, static var compensators and machine drives for sinusoidal and trapezoidal current applications. The drawbacks are the isolated power supplies required for each one of the stages of the multiconverter and it’s also lot harder to build, more expensive, harder to control in software. This project aims at the simulation study of three phase single level and multilevel inverters. The role of inverters in active power filter for harmonic filtering is studied and simulated in MATLAB/SIMULINK. Firstly, the three phase system with non-linear loads are modeled and their characteristics is observed . Secondly, the active power filters are modeled with the inverters and suitable switching control strategies ( PWM technique) to carry out harmonic elimination

Contrôle avancé des convertisseurs de puissance multi-niveaux pour applications sur réseaux faibles

139 p.El advenimiento progresivo de las microrredes que incorporan fuentes de energía renovable está dando lugar a un nuevo paradigma de distribución de la electricidad. Este nuevo planteamiento sirve de interfaz entre consumidores no controlados y fuentes intermitentes, implicando desafíos adicionales en materia de conversión, almacenamiento y gestión de la energía.Los convertidores de potencia se adaptan en consecuencia, en particular con el desarrollo de los convertidores multinivel, que integrando los mismos componentes que sus predecesores y un control más complejo, soportan potencias más altas y aseguran una mejor calidad de la energía.Debido al carácter híbrido de los convertidores de potencia, su control se divide comúnmente en dos partes: por un lado, el control de los objetivos continuos vinculados a la función principal de los convertidores de servir de interfaz, y, por otro, el control discreto de los interruptores de potencia, conocido con el nombre de modulación.En este contexto, las exigencias crecientes en términos de eficiencia, fiabilidad, versatilidad y rendimiento hacen necesaria una mejora de la inteligencia de la estructura de control. Para cumplir conestos requisitos, se propone tratar mediante un solo controlador ambas problemáticas, la vinculada a la función de interfaz de los convertidores y la relacionada con su naturaleza discreta. Esta decisión implica incorporar la no-linealidad de los convertidores de potencia en el controlador, lo que equivale a suprimir el bloque de modulación, que constituye la solución tradicional para linealizar el comportamiento interno de los convertidores. Se adopta un planteamiento de Control Predictivo basado en Modelos (MPC) para abordar la no-linealidad y la gran diversidad de objetivos de control que acompañan a los convertidores de potencia.El algoritmo desarrollado combina teoría de grafos ¿con algoritmos de Dijkstra, A* y otros¿ con un modelo de estado especial para sistemas conmutados al objeto de proporcionar una herramienta potente y universal, capaz de manipular simultáneamente el carácter cuantificado de los interruptores de potencia y el continuo de las entidades interconectadas por el convertidor. Se han obtenido resultados sobre la estabilidad y la controlabilidad de los modelos de estado conmutados aplicados al caso particular de los convertidores de potencia.El controlador así desarrollado y descrito se ha examinado en simulación frente a varios casos y aplicaciones: inversor aislado o conectado a la red, rectificador y convertidor bidireccional. Se ha empleado la misma estructura de control para tres topologías de convertidor multinivel: Neutral-Point Clamped, Flying Capacitor y Cascaded H-Bridge. Al objeto de adaptarse a los cambios citados, lo único que varía en el controlador es el modelo del convertidor adoptado para la predicción, así como la función de coste, que traduce los requisitos de control en un problema de optimización a solucionar por el algoritmo. Un cambio de topología resulta en una modificación del modelo interno, sin impacto sobre la función de coste, mientras que variaciones de esta función son suficientes para adaptarse a la aplicación.Los resultados muestran que el controlador logra actuar directamente sobre los interruptores de potencia en función de diversos requisitos. Los desempeños de la estructura de control propuesta son similares a los de las numerosas estructuras dedicadas a cada uno de los casos estudiados, excepto en el caso de operación en modo rectificador, en el que la versatilidad y rapidez de control obtenidos son particularmente interesantes.En definitiva, el controlador planteado puede emplearse para diferentes aplicaciones, topologías, objetivos y limitaciones. Si bien las estructuras de control lineal tradicionales han de modificarse, a menudo en profundidad, para afrontar diferentes modos de operación o requisitos de control, dichas alteraciones no tienen ningún impacto sobre la arquitectura del controlador MPC obtenido, lo que pone de manifiesto su versatilidad, así como su universalidad, también demostrada por su capacidad para adaptarse a diferentes convertidores de potencia sin modificaciones importantes. Finalmente, la solución propuesta elude por completo la complejidad de la modulación, ofreciendo simplicidad y flexibilidad al diseño del control

Multilevel Converters: An Enabling Technology for High-Power Applications

| Multilevel converters are considered today as the state-of-the-art power-conversion systems for high-power and power-quality demanding applications. This paper presents a tutorial on this technology, covering the operating principle and the different power circuit topologies, modulation methods, technical issues and industry applications. Special attention is given to established technology already found in industry with more in-depth and self-contained information, while recent advances and state-of-the-art contributions are addressed with useful references. This paper serves as an introduction to the subject for the not-familiarized reader, as well as an update or reference for academics and practicing engineers working in the field of industrial and power electronics.Ministerio de Ciencia y Tecnología DPI2001-3089Ministerio de Eduación y Ciencia d TEC2006-0386

A review of modular electrical sub-systems of electric vehicles

Climate change risks have triggered the international community to find efficient solutions to reduce greenhouse gas (GHG) emissions mainly produced by the energy, industrial, and transportation sectors. The problem can be significantly tackled by promoting electric vehicles (EVs) to be the dominant technology in the transportation sector. Accordingly, there is a pressing need to increase the scale of EV penetration, which requires simplifying the manufacturing process, increasing the training level of maintenance personnel, securing the necessary supply chains, and, importantly, developing the charging infrastructure. A new modular trend in EV manufacturing is being explored and tested by several large automotive companies, mainly in the USA, the European Union, and China. This modular manufacturing platform paves the way for standardised manufacturing and assembly of EVs when standard scalable units are used to build EVs at different power scales, ranging from small light-duty vehicles to large electric buses and trucks. In this context, modularising EV electric systems needs to be considered to prepare for the next EV generation. This paper reviews the main modular topologies presented in the literature in the context of EV systems. This paper summarises the most promising topologies in terms of modularised battery connections, propulsion systems focusing on inverters and rectifiers, modular cascaded EV machines, and modular charging systems

Efficiency of Active Three-Level and Five-Level NPC Inverters Compared to a Two-Level Inverter in a Vehicle

This paper deals with a comparison of a standard two-level inverter, with a three-level and a five-level active neutral point clamped (ANPC) inverter for vehicle traction applications. The inverter efficiencies during different drive cycles are assessed and an efficiency enhancement of the multilevel inverters for partial loading and different drive cycle scenarios is found

CMOS current-mode chaotic neurons

This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks, and another circuit to realize programmable current-mode synapse using CMOS-compatible BJT's. They have been fabricated in a double-metal, single-poly 1.6 /spl mu/m CMOS technology and their measured performance reached the expected function and specifications. The neuron soma circuits use a novel, highly accurate CMOS circuit strategy to realize piecewise-linear characteristics in the current-mode domain. Their prototypes obtain reduced area and low voltage power supply (down to 3 V) with clock frequency of 500 kHz. As regard to the synapse circuit, it obtains large linearity and continuous, linear, weight adjustment by exploration of the exponential-law operation of CMOS-BJT's. The full accordance observed between theory and measurements supports the development of future analog VLSI chaotic neural networks to emulate biological systems and advanced computation

Small signal modeling and analysis of microgrid systems

This dissertation focuses on small-signal modeling and analysis of inverter based microgrid systems. The proposed microgrid consists of two microsources placed on two different buses. The buses are connected using a distribution feeder with some impedance. The proposed microgrid can operate with the grid support, or without the grid support. When operated without the grid support, the standalone system’s microsources participate in controlling the system voltage and frequency. For a non-inertia source, such as the inverter, the load perturbations play an important role in system dynamics. In paper-I, such complex system was studied. In the grid-tied mode, the microsources share the load demand with other sources that are present in the main grid. The control algorithm for such system is much simpler than that of the islanded system. However, when aggregated in multi-bus system, prohibitively higher order state-space models are formed. In paper-II, a reduced order modeling of such systems was considered. Singular perturbation method was applied to identify the two time-scale property of the system. In paper-III, a similar approach was taken to develop a reduced order model of the islanded system that was developed in paper-I. Application of such reduced order models were illustrated by using them to simulate a modified IEEE-37 bus microgrid system. The islanded microgrids system’s stability is characterized in paper-IV by the Markov Jump Linear System Analysis. Conservative bounds on the expected value of the state were determined from a combination of the Markov process parameters, the dynamics of each linear system, and the magnitude of the impulses. The conclusions were verified with the simulation results. --Abstract, page iii