Efficient Computation and FPGA implementation of Fully Homomorphic Encryption with Cloud Computing Significance

Homomorphic Encryption provides unique security solution for cloud computing. It ensures not only that data in cloud have confidentiality but also that data processing by cloud server does not compromise data privacy. The Fully Homomorphic Encryption (FHE) scheme proposed by Lopez-Alt, Tromer, and Vaikuntanathan (LTV), also known as NTRU(Nth degree truncated polynomial ring) based method, is considered one of the most important FHE methods suitable for practical implementation. In this thesis, an efficient algorithm and architecture for LTV Fully Homomorphic Encryption is proposed. Conventional linear feedback shift register (LFSR) structure is expanded and modified for performing the truncated polynomial ring multiplication in LTV scheme in parallel. Novel and efficient modular multiplier, modular adder and modular subtractor are proposed to support high speed processing of LFSR operations. In addition, a family of special moduli are selected for high speed computation of modular operations. Though the area keeps the complexity of O(Nn^2) with no advantage in circuit level. The proposed architecture effectively reduces the time complexity from O(N log N) to linear time, O(N), compared to the best existing works. An FPGA implementation of the proposed architecture for LTV FHE is achieved and demonstrated. An elaborate comparison of the existing methods and the proposed work is presented, which shows the proposed work gains significant speed up over existing works

Space time transceiver design over multipath fading channels

Imperial Users onl

Electronic instructional materials and course requirements "Computer science" for specialty: 1-53 01 01 «Automation of technological processes and production»

The purpose of the electronic instructional materials and course requirements by the discipline «Computer science» (EIMCR) is to develop theoretical systemic and practical knowledge in different fields of Computer science. Features of structuring and submission of educational material: EIMCR includes the following sections: theoretical, practical, knowledge control, auxiliary. The theoretical section presents lecture material in accordance with the main sections and topics of the syllabus. The practical section of the EIMCR contains materials for conducting practical classes aimed to develop modern computational thinking, basic skills in computing and making decisions in the field of the fundamentals of computer theory and many computer science fields. The knowledge control section of the EIMCR contains: guidelines for the implementation of the control work aimed at developing the skills of independent work on the course under study, developing the skills of selecting, analyzing and writing out the necessary material, as well as the correct execution of the tasks; list of questions for the credit by the discipline. The auxiliary section of the EIMCR contains the following elements of the syllabus: explanatory note; thematic lectures plan; tables of distribution of classroom hours by topics and informational and methodological part. EIMCR contains active links to quickly find the necessary material

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

Collaborative modulation multiple access for single hop and multihop networks

While the bandwidth available for wireless networks is limited, the world has seen an unprecedented growth in the number of mobile subscribers and an ever increasing demand for high data rates. Therefore efficient utilisation of bandwidth to maximise link spectral efficiency and number of users that can be served simultaneously are primary goals in the design of wireless systems. To achieve these goals, in this thesis, a new non-orthogonal uplink multiple access scheme which combines the functionalities of adaptive modulation and multiple access called collaborative modulation multiple access (CMMA) is proposed. CMMA enables multiple users to access the network simultaneously and share the same bandwidth even when only a single receive antenna is available and in the presence of high channel correlation. Instead of competing for resources, users in CMMA share resources collaboratively by employing unique modulation sets (UMS) that differ in phase, power, and/or mapping structure. These UMS are designed to insure that the received signal formed from the superposition of all users’ signals belongs to a composite QAM constellation (CC) with a rate equal to the sum rate of all users. The CC and its constituent UMSs are designed centrally at the BS to remove ambiguity, maximize the minimum Euclidian distance (dmin) of the CC and insure a minimum BER performance is maintained. Users collaboratively precode their transmitted signal by performing truncated channel inversion and phase rotation using channel state information (CSI ) obtained from a periodic common pilot to insure that their combined signal at the BS belongs to the CC known at the BS which in turn performs a simple joint maximum likelihood detection without the need for CSI. The coherent addition of users’ power enables CMMA to achieve high link spectral efficiency at any time without extra power or bandwidth but on the expense of graceful degradation in BER performance. To improve the BER performance of CMMA while preserving its precoding and detection structure and without the need for pilot-aided channel estimation, a new selective diversity combining scheme called SC-CMMA is proposed. SC-CMMA optimises the overall group performance providing fairness and diversity gain for various users with different transmit powers and channel conditions by selecting a single antenna out of a group of L available antennas that minimises the total transmit power required for precoding at any one time. A detailed study of capacity and BER performance of CMMA and SC-CMMA is carried out under different level of channel correlations which shows that both offer high capacity gain and resilience to channel correlation. SC-CMMA capacity even increase with high channel correlation between users’ channels. CMMA provides a practical solution for implementing the multiple access adder channel (MAAC) in fading environments hence a hybrid approach combining both collaborative coding and modulation referred to as H-CMMA is investigated. H-CMMA divides users into a number of subgroups where users within a subgroup are assigned the same modulation set and different multiple access codes. H-CMMA adjusts the dmin of the received CC by varying the number of subgroups which in turn varies the number of unique constellation points for the same number of users and average total power. Therefore H-CMMA can accommodate many users with different rates while flexibly managing the complexity, rate and BER performance depending on the SNR. Next a new scheme combining CMMA with opportunistic scheduling using only partial CSI at the receiver called CMMA-OS is proposed to combine both the power gain of CMMA and the multiuser diversity gain that arises from users’ channel independence. To avoid the complexity and excessive feedback associated with the dynamic update of the CC, the BS takes into account the independence of users’ channels in the design of the CC and its constituent UMSs but both remain unchanged thereafter. However UMS are no longer associated with users, instead channel gain’s probability density function is divided into regions with identical probability and each UMS is associated with a specific region. This will simplify scheduling as users can initially chose their UMS based on their CSI and the BS will only need to resolve any collision when the channels of two or more users are located at the same region. Finally a high rate cooperative communication scheme, called cooperative modulation (CM) is proposed for cooperative multiuser systems. CM combines the reliability of the cooperative diversity with the high spectral efficiency and multiple access capabilities of CMMA. CM maintains low feedback and high spectral efficiency by restricting relaying to a single route with the best overall channel. Two possible variations of CM are proposed depending on whether CSI available only at the users or just at the BS and the selected relay. The first is referred to Precode, Amplify, and Forward (PAF) while the second one is called Decode, Remap, and Forward (DMF). A new route selection algorithm for DMF based on maximising dmin of random CC is also proposed using a novel fast low-complexity multi-stage sphere based algorithm to calculate the dmin at the relay of random CC that is used for both relay selection and detection

Design Techniques for High Performance Wireline Communication and Security Systems

As the amount of data traffic grows exponentially on the internet, towards thousands of exabytes by 2020, high performance and high efficiency communication and security solutions are constantly in high demand, calling for innovative solutions. Within server communication dominates todays network data transfer, outweighing between-server and server-to-user data transfer by an order of magnitude. Solutions for within-server communication tend to be very wideband, i.e. on the order of tens of gigahertz, equalizers are widely deployed to provide extended bandwidth at reasonable cost. However, using equalizers typically costs the available signal-to-noise ratio (SNR) at the receiver side. What is worse is that the SNR available at the channel becomes worse as data rate increases, making it harder to meet the tight constraint on error rate, delay, and power consumption. In this thesis, two equalization solutions that address optimal equalizer implementations are discussed. One is a low-power high-speed maximum likelihood sequence detection (MLSD) that achieves record energy efficiency, below 10 pico-Joule per bit. The other one is a phase-shaping equalizer design that suppresses inter-symbol interference at almost zero cost of SNR. The growing amount of communication use also challenges the design of security subsystems, and the emerging need for post-quantum security adds to the difficulties. Most of currently deployed cryptographic primitives rely on the hardness of discrete logarithms that could potentially be solved efficiently with a powerful enough quantum computer. Efficient post-quantum encryption solutions have become of substantial value. In this thesis a fast and efficient lattice encryption application-specific integrated circuit is presented that surpasses the energy efficiency of embedded processors by 4 orders of magnitude.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/146092/1/shisong_1.pd

Design of Discrete-time Chaos-Based Systems for Hardware Security Applications

Security of systems has become a major concern with the advent of technology. Researchers are proposing new security solutions every day in order to meet the area, power and performance specifications of the systems. The additional circuit required for security purposes can consume significant area and power. This work proposes a solution which utilizes discrete-time chaos-based logic gates to build a system which addresses multiple hardware security issues. The nonlinear dynamics of chaotic maps is leveraged to build a system that mitigates IC counterfeiting, IP piracy, overbuilding, disables hardware Trojan insertion and enables authentication of connecting devices (such as IoT and mobile). Chaos-based systems are also used to generate pseudo-random numbers for cryptographic applications.The chaotic map is the building block for the design of discrete-time chaos-based oscillator. The analog output of the oscillator is converted to digital value using a comparator in order to build logic gates. The logic gate is reconfigurable since different parameters in the circuit topology can be altered to implement multiple Boolean functions using the same system. The tuning parameters are control input, bifurcation parameter, iteration number and threshold voltage of the comparator. The proposed system is a hybrid between standard CMOS logic gates and reconfigurable chaos-based logic gates where original gates are replaced by chaos-based gates. The system works in two modes: logic locking and authentication. In logic locking mode, the goal is to ensure that the system achieves logic obfuscation in order to mitigate IC counterfeiting. The secret key for logic locking is made up of the tuning parameters of the chaotic oscillator. Each gate has 10-bit key which ensures that the key space is large which exponentially increases the computational complexity of any attack. In authentication mode, the aim of the system is to provide authentication of devices so that adversaries cannot connect to devices to learn confidential information. Chaos-based computing system is susceptible to process variation which can be leveraged to build a chaos-based PUF. The proposed system demonstrates near ideal PUF characteristics which means systems with large number of primary outputs can be used for authenticating devices

The 1992 4th NASA SERC Symposium on VLSI Design

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design