Design of Dual Dynamic Flip-Flop with Featuring Efficient Embedded Logic for Low Power Cmos Vlsi Circuits

In this paper, we introduce a new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded \ud logic module (DDFF-ELM) based on DDFF. The proposed designs eliminate the large capacitance present in \ud the pre-charge node of several state-of-the-art designs by following a split dynamic node structure to separately \ud drive the output pull-up and pull down transistors. The aim of the DDFF-ELM is to reduce pipeline overhead. It \ud presents an area, power, and speed efficient method to incorporate complex logic functions into the flip-flop. \ud The performance comparisons made in a 90 nm technology when compared to the Semi dynamic flip-flop, with \ud no degradation in speed performance. The leakage power and process-voltage-temperature variations of various \ud designs are studied in detail and are compared with the proposed designs