Parity Codes Used for On-Line Testing in FPGA

This paper deals with on-line error detection in digital circuits implemented in FPGAs. Error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit must be detected and signalized at the time of its appearance and before further distribution of errors. Hence safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. Combinational circuit benchmarks have been used in this work in order to compute the quality of the proposed codes. The description of the benchmarks is based on equations and tables. All of our experimental results are obtained by XILINX FPGA implementation EDA tools. A possible TSC structure consisting of several TSC blocks is presented.

Concurrent Fault Detection in Random Combinational Logic

We discuss a non-intrusive methodology for concurrent fault detection in random combinational logic. The proposed method is similar to duplication, wherein a replica of the circuit acts as a predictor that immediately detects potential faults by comparison to the original circuit. However, instead of duplicating the circuit, the proposed method selects a small number of prediction logic functions which only partially replicate it. Selection is guided by the objective of minimizing the incurred hardware overhead at the cost of introducing fault detection latency. To achieve this, the proposed method replicates only a reduced width output function for every input combination, yet without compromising the ability to detect all faults. In contrast to concurrent error detection schemes which presume the ability to re-synthesize the circuit, the proposed method does not interfere with the implementation of the original design. As compared to previous approaches, the proposed method achieves significant hardware overhead reduction, while detecting all faults with very low average fault detection latency. 1