Concept and Design of Exhaustive-Parallel search algorithm for Network-on-Chip

Abstract: This paper presents the concept and design of exhaustive-parallel search algorithm for Networkon-Chip. The proposed parallel algorithm searches minimal path between source and destination in a forward-wave-propagation manner. The algorithm guarantees setup latency if the setup path exists. A high performance switch is designed to support exhaustive-parallel search algorithm. The NoC fabric is designed for 8X8 mesh architecture and its performance is evaluated