Enabling high-performance, mixed-signal approximate computing

textFor decades, the semiconductor industry enjoyed exponential improvements in microprocessor power and performance with the device scaling of successive technology generations. Scaling limitations at sub-micron technologies, however, have ceased to provide these historical performance improvements within a limited power budget. While device scaling provides a larger number of transistors per chip, for the same chip area, a growing percentage of the chip will have to be powered off at any given time due to power constraints. As such, the architecture community has focused on energy-efficient designs and is looking to specialized hardware to provide gains in performance. A focus on energy efficiency, along with increasingly less reliable transistors due to device scaling, has led to research in the area of approximate computing, where accuracy is traded for energy efficiency when precise computation is not required. There is a growing body of approximation-tolerant applications that, for example, compute on noisy or incomplete data, such as real-world sensor inputs, or make approximations to decrease the computation load in the analysis of cumbersome data sets. These approximation-tolerant applications span application domains, such as machine learning, image processing, robotics, and financial analysis, among others. Since the advent of the modern processor, computing models have largely presumed the attribute of accuracy. A willingness to relax accuracy requirements, however, with goal of gaining energy efficiency, warrants the re-investigation of the potential of analog computing. Analog hardware offers the opportunity for fast and low-power computation; however, it presents challenges in the form of accuracy. Where analog compute blocks have been applied to solve fixed-function problems, general-purpose computing has relied on digital hardware implementations that provide generality and programmability. The work presented in this thesis aims to answer the following questions: Can analog circuits be successfully integrated into general-purpose computing to provide performance and energy savings? And, what is required to address the historical analog challenges of inaccuracy, programmability, and a lack of generality to enable such an approach? This thesis work investigates a neural approach as a means to address the historical analog challenges of inaccuracy, programmability, and generality and to enable the use of analog circuits in general-purpose, high-performance computing. The first piece of this thesis work investigates the use of analog circuits at the microarchitecture level in the form of an analog neural branch predictor. The task of branch prediction can tolerate imprecision, as roll-back mechanisms correct for branch mispredictions, and application-level accuracy remains unaffected. We show that analog circuits enable the implementation of a highly-accurate, neural-prediction algorithm that is infeasible to implement in the digital domain. The second piece of this thesis work presents a neural accelerator that targets approximation-tolerant code. Analog neural acceleration provides application speedup of 3.3x and energy savings of 12.1x with a quality loss less than 10% for all except one approximation-tolerant benchmark. These results show that, using a neural approach, analog circuits can be applied to provide performance and energy efficiency in high-performance, general-purpose computing.Computer Science

Principled Approaches to Last-Level Cache Management

Memory is a critical component of all computing systems. It represents a fundamental performance and energy bottleneck. Ideally, memory aspects such as energy cost, performance, and the cost of implementing management techniques would scale together with the size of all different computing systems; unfortunately this is not the case. With the upcoming trends in applications, new memory technologies, etc., scaling becomes a bigger a problem, aggravating the performance bottleneck that memory represents. A memory hierarchy was proposed to alleviate the problem. Each level in the hierarchy tends to have a decreasing cost per bit, an increased capacity, and a higher access time compared to its previous level. Preferably all data will be stored in the fastest level of memory, unfortunately, faster memory technologies tend to be associated with a higher manufacturing cost, which often limits their capacity. The design challenge is, to determine which is the frequently used data, and store it in the faster levels of memory. A cache is a small, fast, on-chip chunk of memory. Any data stored in main memory can be stored in the cache. For many programs, a typical behavior is to access data that has been accessed previously. Taking advantage of this behavior, a copy of frequently accessed data is kept in the cache, in order to provide a faster access time next time is requested. Due to capacity constrains, it is likely that all of the frequently reused data cannot fit in the cache, because of this, cache management policies decide which data is to be kept in the cache, and which in other levels of the memory hierarchy. Under an efficient cache management policy, an encouraging amount of memory requests will be serviced from a fast on-chip cache. The disparity in access latency between the last-level cache and main memory motivates the search for efficient cache management policies. There is a great amount of recently proposed work that strives to utilize cache capacity in the most favorable to performance way possible. Related work focus on optimizing the performance of caches focusing on different possible solutions, e.g. reduce miss rate, consume less power, reducing storage overhead, reduce access latency, etc. Our work focus on improving the performance of last-level caches by designing policies based on principles adapted from other areas of interest. In this dissertation, we focus on several aspects of cache management policies, we first introduce a space-efficient placement and promotion policy which goal is to minimize the updates to the replacement policy state on each cache access. We further introduce a mechanism that predicts whether a block in the cache will be reused, it feeds different features from a block to the predictor in order to increase the correlation of a previous access to a future access. We later introduce a technique that tweaks traditional cache indexing, providing fast accesses to a vast majority of requests in the presence of a slow access memory technology such as DRAM

Summarizing multiprocessor program execution with versatile, microarchitecture-independent snapshots

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 131-137).Computer architects rely heavily on software simulation to evaluate, refine, and validate new designs before they are implemented. However, simulation time continues to increase as computers become more complex and multicore designs become more common. This thesis investigates software structures and algorithms for quickly simulating modern cache-coherent multiprocessors by amortizing the time spent to simulate the memory system and branch predictors. The Memory Timestamp Record (MTR) summarizes the directory and cache state of a multiprocessor system in a compact data structure. A single MTR snapshot is versatile enough to reconstruct the microarchitectural state resulting from various coherence protocols and cache organizations. The MTR may be quickly updated by each simulated processor during a fast-forwarding phase and optionally stored off-line for reuse. To fill large branch prediction tables, we introduce Branch Predictor-based Compression (BPC) which compactly stores a branch trace so that it may be used to fill in any branch predictor structure. An entire BPC trace requires less space than single discrete predictor snapshots, and it may be decompressed 3-6x faster than performing functional simulation.by Kenneth C. Barr.Ph.D

Portugal SB13: contribution of sustainable building to meet EU 20-20-20 targets

Proceedings of the International Conference Portugal SB13: contribution of sustainable building to meet EU 20-20-20 targetsThe international conference Portugal SB13 is organized by the University of Minho, the Technical University of Lisbon and the Portuguese Chapter of the International Initiative for a Sustainable Built Environment in Guimarães, Portugal, from the 30th of October till the 1st of November 2013. This conference is included in the Sustainable Building Conference Series 2013-2014 (SB13-14) that are being organized all over the world. The event is supported by high prestige partners, such as the International Council for Research and Innovation in Building and Construction (CIB), the United Nations Environment Programme (UNEP), the International Federation of Consulting Engineers (FIDIC) and the International Initiative for a Sustainable Built Environment (iiSBE). Portugal SB13 is focused on the theme â Sustainable Building Contribution to Achieve the European Union 20-20-20 Targetsâ . These targets, known as the â EU 20-20-20â targets, set three key objectives for 2020: - A 20% reduction in EU greenhouse gas emissions from 1990 levels; - Raising the share of EU energy consumption produced from renewable resources to 20%; - A 20% improvement in the EU's energy efficiency. Building sector uses about 40% of global energy, 25% of global water, 40% of global resources and emit approximately 1/3 of the global greenhouse gas emissions (the largest contributor). Residential and commercial buildings consume approximately 60% of the worldâ s electricity. Existing buildings represent significant energy saving opportunities because their performance level is frequently far below the current efficiency potentials. Energy consumption in buildings can be reduced by 30 to 80% using proven and commercially available technologies. Investment in building energy efficiency is accompanied by significant direct and indirect savings, which help offset incremental costs, providing a short return on investment period. Therefore, buildings offer the greatest potential for achieving significant greenhouse gas emission reductions, at least cost, in developed and developing countries. On the other hand, there are many more issues related to the sustainability of the built environment than energy. The building sector is responsible for creating, modifying and improving the living environment of the humanity. Construction and buildings have considerable environmental impacts, consuming a significant proportion of limited resources of the planet including raw material, water, land and, of course, energy. The building sector is estimated to be worth 10% of global GDP (5.5 trillion EUR) and employs 111 million people. In developing countries, new sustainable construction opens enormous opportunities because of the population growth and the increasing prosperity, which stimulate the urbanization and the construction activities representing up to 40% of GDP. Therefore, building sustainably will result in healthier and more productive environments. The sustainability of the built environment, the construction industry and the related activities are a pressing issue facing all stakeholders in order to promote the Sustainable Development. The Portugal SB13 conference topics cover a wide range of up-to-date issues and the contributions received from the delegates reflect critical research and the best available practices in the Sustainable Building field. The issues presented include: - Nearly Zero Energy Buildings - Policies for Sustainable Construction - High Performance Sustainable Building Solutions - Design and Technologies for Energy Efficiency - Innovative Construction Systems - Building Sustainability Assessment Tools - Renovation and Retrofitting - Eco-Efficient Materials and Technologies - Urban Regeneration - Design for Life Cycle and Reuse - LCA of sustainable materials and technologies All the articles selected for presentation at the conference and published in these Proceedings, went through a refereed review process and were evaluated by, at least, two reviewers. The Organizers want to thank all the authors who have contributed with papers for publication in the proceedings and to all reviewers, whose efforts and hard work secured the high quality of all contributions to this conference. A special gratitude is also addressed to Eng. José Amarílio Barbosa and to Eng. Catarina Araújo that coordinated the Secretariat of the Conference. Finally, Portugal SB13 wants to address a special thank to CIB, UNEP, FIDIC and iiSBE for their support and wish great success for all the other SB13 events that are taking place all over the world

Energy. A continuing bibliography with indexes, issue 36, January 1983

This bibliography lists 1297 reports, articles, and other documents introduced into the NASA scientific and technical information system from October 1, 1982 through December 31, 1982