35 research outputs found

    Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

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    The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

    Lower Bound for the Duration of Event Sequences of Given Length in Timed Discrete Event Systems

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    The Supervisory Control Theory (SCT) of Discrete Event Systems (DES) provides a framework for synthesizing a DES supervisor to ensure a DES plant satisfies its design specification. In SCT, supervisor synthesis is performed offline before the functioning of the plant. Generally, the size of the plant and the specifications models are large resulting in supervisors that need huge computer memory for storage -- usually unavailable in embedded systems. A solution to this problem proposed in the literature is Limited Lookahead Policy (LLP). In LLP, the supervisory control commands are calculated online during the plant operation. After the occurrence of each event, the next control command is calculated based on the plant behaviour over a limited number of events into the future. In practice such frequent LLP computation would not be feasible as multiple events can occur consecutively over a short duration, not leaving enough time for LLP computation between them. To tackle this issue, a method is proposed called LLP with Buffering where the supervisory control commands are calculated online and buffered in advance for a predefined window of events in future. Determining the correct size of the buffer is crucial in order to achieve a trade-off between the on-board memory requirement and the computational resources and also ensuring that new supervisor commands are computed before the buffer runs out empty. The size of the buffer primarily depends on (1) the execution time of the code for supervisor calculation and (2) the (fastest) rate of event generation in the plant. This thesis focuses on the second factor. Previously, the minimum execution duration of event sequences has been calculated experimentally. The experimental approach is not exhaustive and thus results in an overestimate in the value of the minimum execution duration of event sequences. In this thesis, a model-based approach to the computation of the minimum duration is proposed which begins by transforming the untimed model of the plant under supervision into a timed automaton (TA) by incorporating timing information of the events. Next, an exhaustive symbolic matrix-based search algorithm is proposed where all the event sequences from every mode of the TA model are traversed to determine the minimum execution duration of the event sequences. The proposed method avoids the reachability analysis of TA needed to determine the reachable clock regions for each mode. The number of these regions is exponential in the number of events. Instead, the method uses reachability on the graph of the untimed model (polynomial in the number of events). This algorithm runs faster but provides an underestimate for the minimum execution duration of event sequences. Next, a two-degree-of-freedom solar tracker system is used as a plant to analyse the timing behaviour of the events and the implementation of LLP with buffering. In this study, the model-based and experimental methods have been used together to choose a suitable buffer size. The resulting LLP supervisor with buffering has been successfully implemented

    Computer Aided Verification

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    This open access two-volume set LNCS 10980 and 10981 constitutes the refereed proceedings of the 30th International Conference on Computer Aided Verification, CAV 2018, held in Oxford, UK, in July 2018. The 52 full and 13 tool papers presented together with 3 invited papers and 2 tutorials were carefully reviewed and selected from 215 submissions. The papers cover a wide range of topics and techniques, from algorithmic and logical foundations of verification to practical applications in distributed, networked, cyber-physical, and autonomous systems. They are organized in topical sections on model checking, program analysis using polyhedra, synthesis, learning, runtime verification, hybrid and timed systems, tools, probabilistic systems, static analysis, theory and security, SAT, SMT and decisions procedures, concurrency, and CPS, hardware, industrial applications

    Programming Languages and Systems

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    This open access book constitutes the proceedings of the 29th European Symposium on Programming, ESOP 2020, which was planned to take place in Dublin, Ireland, in April 2020, as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2020. The actual ETAPS 2020 meeting was postponed due to the Corona pandemic. The papers deal with fundamental issues in the specification, design, analysis, and implementation of programming languages and systems

    FInCo 2007 AGAPIA v0.1: A programming language for interactive systems and its typing system

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    Abstract A model (consisting of rv-systems), a core programming language (for developing rv-programs), several specification and analysis techniques appropriate for modeling, programming and reasoning about interactive computing systems have been recently introduced by Stefanescu using register machines and space-time duality, se

    Session-based concurrency: between operational and declarative views

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    Communication-based software is ubiquitous nowadays. From e-banking to e-shopping, online activities often involve message exchanges between software components. These interactions are often governed by protocols that explicitly describe the sequences of communication actions that should be executed by each component. Crucially, these protocols are not isolated from a program’s context: external conditions such as timing constraints or exceptional events that occur during execution can affect message exchanges. As an additional difficulty, individual components are typically developed in different programming languages. In this setting, certifying that a program conforms to its intended protocols is challenging. A widely studied program verification technique uses behavioral type systems, which exploit abstract representations of these protocols to check that the program executes communication actions as intended. Unfortunately, the abstractions offered by behavioral type systems may neglect the influence that external conditions have on the program. This thesis addresses this issue by considering programming languages with declarative features, in which the governing conditions of the program can be adequately described. Our work develops correct translations between programming languages to show that languages with declarative features can indeed articulate a unified view of communication-based programs. Specifically, these translations demonstrate that the operational features of communication-based programs can be correctly represented by languages with declarative features. An additional contribution is a hybrid language that combines the best of both worlds, enabling the analysis of operational and declarative features in communication-based programs

    Supervisory control synthesis for large-scale infrastructural systems

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    Supervisory control synthesis for large-scale infrastructural systems

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    Reasoning with time and data abstractions

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    In this thesis, we address the problem of verifying the functional correctness of concurrent programs, with emphasis on fine-grained concurrent data structures. Reasoning about such programs is challenging since data can be concurrently accessed by multiple threads: the reasoning must account for the interference between threads, which is often subtle. To reason about interference, concurrent operations should either be at distinct times or on distinct data. We present TaDA, a sound program logic for verifying clients and implementations that use abstract specifications that incorporate both abstract atomicity—the abstraction that operations take effect at a single, discrete instant in time—and abstract disjointness—the abstraction that operations act on distinct data resources. Our key contribution is the introduction of atomic triples, which offer an expressive approach for specifying program modules. We also present Total-TaDA, a sound extension of TaDA with which we can verify total correctness of concurrent programs, i.e. that such programs both produce the correct result and terminate. With Total-TaDA, we can specify constraints on a thread’s concurrent environment that are necessary to guarantee termination. This allows us to verify total correctness for nonblocking algorithms and express lock- and wait-freedom. More generally, the abstract specifications can express that one operation cannot impede the progress of another, a new non-blocking property that we call non-impedance. Finally, we describe how to extend TaDA for proving abstract atomicity for data structures that make use of helping—where one thread is performing an abstract operation on behalf of another—and speculation—where an abstract operation is determined by future behaviour.Open Acces

    Model Checking and Model-Based Testing : Improving Their Feasibility by Lazy Techniques, Parallelization, and Other Optimizations

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    This thesis focuses on the lightweight formal method of model-based testing for checking safety properties, and derives a new and more feasible approach. For liveness properties, dynamic testing is impossible, so feasibility is increased by specializing on an important class of properties, livelock freedom, and deriving a more feasible model checking algorithm for it. All mentioned improvements are substantiated by experiments
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