Analogue circuits for low power communication

Low power electronic circuits are required to extend the operational time of battery operated devices. They are also necessary to reduce the power consumption of equipment in general, especially as the world tries to cut energy usage. The first section of this thesis explores fundamental and implementation limits for low power circuits. The energy requirements of amplification are presented and a lower bound on the energy required to transmit information over a point to point link is proposed. It is evident from the low power limits survey that when a transistor is biased, significant thermodynamic energy is required to reduce the resistance of the channel. A transmitter is presented that turns on a transistor for 0.1 % of transmitted time. This transmitter approximates a Gaussian pulse by allowing the impulse response of two 2nd order transmitting elements to sum in free space. The transmitter is of low complexity and the receiver architecture ensures that no on-line tuning is required. Measured results indicate that by using coherent detection a 1 Mbps, 50 mm distance link with a bit error rate of 10−3 can be achieved. The bandwidth of the transmitted pulse is 30-37.5 MHz and 30 dB of out of band attenuation is provided. An analogue Gabor transform is described which splits a signal into parallel paths of a lower bandwidth. This enables post processing at lower clock rates, which can reduce energy dissipation. An implementation of the transform using sub-threshold CMOS continuous time filters is presented. A novel method for designing low power gmC filters using simple models of identical transconductors is used to specify transistor sizes. Measured results show that the transform consumes 7 μW for an input signal bandwidth of 4 kHz

Complexity reduction in an nRERL microprocessor

We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers required for the phase aligning in the adiabatic microprocessor. Furthermore, by breaking the logic reversibility with self-energy recovery circuits, we also reduced its complexity as well as its energy consumption. We integrated an 8-bit nRERL microprocessor with an 8-phase clocked power generator into a chip with 0.25μm CMOS technology. Its minimum energy consumption of 4.67μA/MHz was measured at Vdd=2.4V and f=651kHz, which was about 40% compared to the previous 6-phase version. Its circuit complexity was also reduced down to 65% that of its 6-phase version