A Fault-tolerant Structure for Reliable Multi-core Systems Based on Hardware-Software Co-design

To cope with the soft errors and make full use of the multi-core system, this paper gives an efficient fault-tolerant hardware and software co-designed architecture for multi-core systems. And with a not large number of test patterns, it will use less than 33% hardware resources compared with the traditional hardware redundancy (TMR) and it will take less than 50% time compared with the traditional software redundancy (time redundant).Therefore, it will be a good choice for the fault-tolerant architecture for the future high-reliable multi-core systems.Comment: 7 pages, 5 figure

Design and Analysis of 2oo3 Static Voter for SMT function in an Adjustable Speed Electrical Power Drive System

In fail-safe systems, a 2-out-of-3 voter is responsible for processing the monitoring of failures of the sensor unit in the system. When a failure has occurred and the outputs directly drive the vital units, there may be some injuries, loss or damages, such as in a nuclear reactor shutdown, railway signalling systems, industrial compression systems, or electric motor drive systems. This paper presents an innovatively designed and developed 2-out-of-3 static voter that detects the signal with a window comparator circuit related to the safety system for the detection of false signals. The voting function is mainly one diode and four optoelectronic switches, which reduces the number of devices, resulting in a lower failure rate. Failure of the voter is detected and corrected by the window comparator with digital switching levels, which is a very simple circuit that is used with low voltage and fast varying input. Furthermore, the analysis of the performance was conducted for IEC 61800-5-2 in an adjustable speed electrical power drive system, with the simulation of the failure rate of electronic equipment, mean time to failure, failure mode and effects analysis (FMEA), and the experimental circuit