Dottie’s Story: Teaching Complex Instruction

Analyzing the structures that frame classroom interactions and learning, and designing, implementing, and analyzing a Complex Instruction (CI) rotation were two requirements for completion of the senior seminar I taught to elementary education majors from 2002-2009. Dottie’s Story relates how the seminar was organized and how one student, Dottie, implemented and reflected upon her learning and the learning of her students. Upon reading this paper, the reader will have a good understanding of how undergraduates were taught CI. We see the various steps of Dottie’s progress through her reflective journal and note the academic and social effects of her work on several students in the kindergarten classroom in which she was a student teacher. Small sample T-tests showed significant academic gains for students in this classroom and qualitative analyses point out the value of status interventions for four students in this classroom. This paper is one chapter in an unpublished book manuscript written during my final sabbatical leave at the University of Vermont

Instruction Set Architectures for Quantum Processing Units

Progress in quantum computing hardware raises questions about how these devices can be controlled, programmed, and integrated with existing computational workflows. We briefly describe several prominent quantum computational models, their associated quantum processing units (QPUs), and the adoption of these devices as accelerators within high-performance computing systems. Emphasizing the interface to the QPU, we analyze instruction set architectures based on reduced and complex instruction sets, i.e., RISC and CISC architectures. We clarify the role of conventional constraints on memory addressing and instruction widths within the quantum computing context. Finally, we examine existing quantum computing platforms, including the D-Wave 2000Q and IBM Quantum Experience, within the context of future ISA development and HPC needs.Comment: To be published in the proceedings in the International Super Computing Conference 2017 publicatio

Liveness-Driven Random Program Generation

Randomly generated programs are popular for testing compilers and program analysis tools, with hundreds of bugs in real-world C compilers found by random testing. However, existing random program generators may generate large amounts of dead code (computations whose result is never used). This leaves relatively little code to exercise a target compiler's more complex optimizations. To address this shortcoming, we introduce liveness-driven random program generation. In this approach the random program is constructed bottom-up, guided by a simultaneous structural data-flow analysis to ensure that the generator never generates dead code. The algorithm is implemented as a plugin for the Frama-C framework. We evaluate it in comparison to Csmith, the standard random C program generator. Our tool generates programs that compile to more machine code with a more complex instruction mix.Comment: Pre-proceedings paper presented at the 27th International Symposium on Logic-Based Program Synthesis and Transformation (LOPSTR 2017), Namur, Belgium, 10-12 October 2017 (arXiv:1708.07854

Reflections on the Practicality of Good Theory

Jennifer Kennison noticed something different about the way her high school chemistry students were working together during Complex Instruction rotation. Her attention to the change in her students’ learning caused me to think about how Elizabeth Cohen’s often referenced Kurt Lewin’s comment “There is nothing so practical as a good theory.” As a result, I decided to ask two students who were teaching CI rotations if they would be interested in working together on a conference presentation that looked at their work through the eyes of Lewin’s dictum. They would take on responsibility for documenting and writing about their CI units and I, their advisor, would take on Lewin. Both Jennifer, an experienced teacher and MEd. candidate, and Bethany Brodeur, a senior elementary education major, agreed to this task. The resulting papers formed the core of our presentation at the 2004 conference of the New England Educational Research Organization. Together, they form a short volume that integrates learning about CI with the practical implications of implementation of CI at the elementary and secondary levels. This paper reports my observations of their work confirming Lewin’s dictum and Cohen’s wisdom. C

Ithemal: Accurate, Portable and Fast Basic Block Throughput Estimation using Deep Neural Networks

Predicting the number of clock cycles a processor takes to execute a block of assembly instructions in steady state (the throughput) is important for both compiler designers and performance engineers. Building an analytical model to do so is especially complicated in modern x86-64 Complex Instruction Set Computer (CISC) machines with sophisticated processor microarchitectures in that it is tedious, error prone, and must be performed from scratch for each processor generation. In this paper we present Ithemal, the first tool which learns to predict the throughput of a set of instructions. Ithemal uses a hierarchical LSTM--based approach to predict throughput based on the opcodes and operands of instructions in a basic block. We show that Ithemal is more accurate than state-of-the-art hand-written tools currently used in compiler backends and static machine code analyzers. In particular, our model has less than half the error of state-of-the-art analytical models (LLVM's llvm-mca and Intel's IACA). Ithemal is also able to predict these throughput values just as fast as the aforementioned tools, and is easily ported across a variety of processor microarchitectures with minimal developer effort.Comment: Published at 36th International Conference on Machine Learning (ICML) 201

Emulation of a Complex Instruction Set Computer with a Reduced Instruction Set Computer

This paper analyzes some of the difficulties of emulating a Complex Instruction Set Computer (CISC) with a Reduced Instruction Set Computer (RISC). It will be shown that although the speed advantage of a RISC is sacrificed, a CISC can be emulated with the exception of software constructs that support nonstandard hardware interfaces. Some concrete examples will be used to help illustrate the execution- time bottlenecks as well as to discuss possible solutions from an architectural point of view for both Silicon and Gallium Arsenide (GaAs). In addition, it will be shown that the most efficient method of emulation involves debugging compiled High-Level Language (HLL) source code on a CISC, and then recompiling the HLL code with a compiler that is familiar with the target RISC architectur

Reducing a complex instruction set computer.

Tse Tin-wah.Thesis (M.Ph.)--Chinese University of Hong Kong, 1988.Bibliography: leaves [73]-[78