Spatially structured oscillations in a two-dimensional excitatory neuronal network with synaptic depression

We study the spatiotemporal dynamics of a two-dimensional excitatory neuronal network with synaptic depression. Coupling between populations of neurons is taken to be nonlocal, while depression is taken to be local and presynaptic. We show that the network supports a wide range of spatially structured oscillations, which are suggestive of phenomena seen in cortical slice experiments and in vivo. The particular form of the oscillations depends on initial conditions and the level of background noise. Given an initial, spatially localized stimulus, activity evolves to a spatially localized oscillating core that periodically emits target waves. Low levels of noise can spontaneously generate several pockets of oscillatory activity that interact via their target patterns. Periodic activity in space can also organize into spiral waves, provided that there is some source of rotational symmetry breaking due to external stimuli or noise. In the high gain limit, no oscillatory behavior exists, but a transient stimulus can lead to a single, outward propagating target wave

Involvement of the proteasome and caspase activation in hippocampal long-term depression induced by the serine protease subtilisin

The serine protease subtilisin-A produces a long-term depression (LTD) of synaptic potentials in hippocampal slices which differs mechanistically from classical LTD. Since caspases have been implicated in hippocampal plasticity, this study examined a possible role for these enzymes in subtilisin-induced LTD. Subtilisin produced a concentration-dependent decrease in the size of field excitatory synaptic potentials (fEPSPs), which was not prevented or modified by the caspase inhibitors Z-VAD(OMe)-fmk and Z-DEVD-fmk. Similarly Z-VAD(OMe)-fmk did not modify the selective loss of protein expression produced by subtilisin. Subtilisin reduced the expression of procaspase-3 and caspase-9 but, while caspase-9 was converted to its conventionally activated form (39 kDa), caspase-3 was metabolised along a non-canonical pathway to a 29/30 kDa protein rather than the classical 17/19 kDa fragments. Both Z-VAD(OMe)-fmk and Z-DEVD-fmk were unable to prevent the reduced expression of Postsynaptic Density Protein-95, Vesicle-Associated Membrane Protein-1 and Unco-ordinated 5H3 proteins produced by subtilisin, although MG132 did produce partial recovery from subtilisin-induced depression of fEPSPs. When tested on long-term potentiation (LTP) induced by theta stimulation in the stratum radiatum, MG132 inhibited the immediate increase in fEPSP size but generated a higher plateau LTP. Twin LTP stimulation generated a further increase in LTP amplitude in control slices but not in slices exposed to MG132. The results indicate that subtilisin does produce caspase activation but that this does not contribute to its induction of LTD. However, activation of the proteasome does contribute to subtilisin-induced LTD and may also play a modulatory role in electrically induced LTP

Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition

A neuromorphic chip that combines CMOS analog spiking neurons and memristive synapses offers a promising solution to brain-inspired computing, as it can provide massive neural network parallelism and density. Previous hybrid analog CMOS-memristor approaches required extensive CMOS circuitry for training, and thus eliminated most of the density advantages gained by the adoption of memristor synapses. Further, they used different waveforms for pre and post-synaptic spikes that added undesirable circuit overhead. Here we describe a hardware architecture that can feature a large number of memristor synapses to learn real-world patterns. We present a versatile CMOS neuron that combines integrate-and-fire behavior, drives passive memristors and implements competitive learning in a compact circuit module, and enables in-situ plasticity in the memristor synapses. We demonstrate handwritten-digits recognition using the proposed architecture using transistor-level circuit simulations. As the described neuromorphic architecture is homogeneous, it realizes a fundamental building block for large-scale energy-efficient brain-inspired silicon chips that could lead to next-generation cognitive computing.Comment: This is a preprint of an article accepted for publication in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol 5, no. 2, June 201

Hardware design of LIF with Latency neuron model with memristive STDP synapses

In this paper, the hardware implementation of a neuromorphic system is presented. This system is composed of a Leaky Integrate-and-Fire with Latency (LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL neuron model allows to encode more information than the common Integrate-and-Fire models, typically considered for neuromorphic implementations. In our system LIFL neuron is implemented using CMOS circuits while memristor is used for the implementation of the STDP synapse. A description of the entire circuit is provided. Finally, the capabilities of the proposed architecture have been evaluated by simulating a motif composed of three neurons and two synapses. The simulation results confirm the validity of the proposed system and its suitability for the design of more complex spiking neural network